Simultaneous Multithreading Cache Segmentation for Resource Aggressive Applications

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Solution Overview

Problem

Modern computing systems with multiprocessing and simultaneous multithreading often experience cache thrashing due to resource aggressive applications, leading to reduced performance.

Innovation Solution

A system daemon is used to balance resource aggressive applications across system resources by obtaining resource and process information, redistributing processes based on measurements, and offlineing sibling resources to minimize cache thrashing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple virtual logical processors share caches in a simultaneous multithreading system, then system resource utilization is improved, but cache thrashing occurs leading to reduced performance

Engineering Contradiction:
Improvesystem resource utilizationVSAvoidperformance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the cache memory into separate cache spaces associated with different physical processors. Each physical processor has its own dedicated cache space, preventing other processors from accessing or interfering with it. This segmentation eliminates cache thrashing while allowing multiple processors to operate simultaneously, resolving the contradiction between resource utilization and performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a cache space as an intermediary structure between physical processors and main memory. Each physical processor gets a dedicated cache space that acts as a buffer, isolating cache accesses to specific processors and preventing the cache thrashing phenomenon that would otherwise occur when multiple processors share the same cache.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If resource aggressive applications are allowed to execute on multiple logical processors, then parallelization capability is improved, but cache interference increases

Engineering Contradiction:
Improveparallelization capabilityVSAvoidcache interference
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments cache resources by physically associating dedicated cache spaces with each physical processor. This ensures that even when multiple logical processors execute resource aggressive applications, they cannot interfere with each other's cache spaces, eliminating cache interference while preserving parallelization capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by giving each physical processor exclusive access to its own cache space. This localized cache access pattern ensures that cache behavior is optimized for each individual processor's workload, preventing the harmful cache interference that would occur with shared caches.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If unscalable processes are allocated to shared resources, then system flexibility is improved, but cache thrashing occurs

Engineering Contradiction:
Improvesystem flexibilityVSAvoidapplication performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments cache access rights by physically binding dedicated cache spaces to each physical processor. When unscalable processes are allocated to physical processors, they automatically receive exclusive access to that processor's dedicated cache space, eliminating cache thrashing while maintaining system flexibility in process allocation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dedicated cache space acts as an intermediary that isolates unscalable processes from cache interference. Even though these processes run on shared physical hardware, the dedicated cache space mediates their memory accesses, preventing thrashing and maintaining performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8806504B2Leveraging performance of resource aggressive applications
Publication Date: 2014.08.12 RED HAT INC
  • US8806504B2 patent drawing
  • US8806504B2 patent drawing
  • US8806504B2 patent drawing

AI summary

A simultaneous multithreading computing system obtains process information for the simultaneous multithreading computing system. The process information comprises a plurality of processes associated with the simultaneous multithreading computing system. The simultaneous multithreading computing system obtains resource information for the simultaneous multithreading computing system. The resource information comprises a plurality of available resources in the simultaneous multithreading system. The simultaneous multithreading computing system determines that a process from the plurality of processes is unscalable on the simultaneous multithreading computing system. Upon determining that the process is unscalable, the simultaneous multithreading computing system selects a resource to execute the unscalable process based on the resource information. Upon determining that a sibling resource is associated with the selected resource, the simultaneous multithreading computing system disconnects the sibling resource.