Multi-Level Cache Hierarchy with Selector Array
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Inclusive multi-level cache structures in modern microprocessors require more chip space and consume excessive power due to duplicated data in higher-level caches, which rarely improves performance in multi-core systems.
Innovation Solution
A multi-level cache structure is designed with a hierarchical configuration that includes a tag array, a selector array, and a data array, where the selector array indicates which data entries are present in the data array, reducing the size of the data array in higher-level caches while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If inclusive multi-level cache structures are used, then data access performance may be improved when lower-level cache data is invalid, but chip space and power consumption increase significantly
Solution Approach 1:
The patent extracts only the necessary metadata (selector array and tag array) from the traditional inclusive cache structure, separating the data storage function from the metadata management function. This allows the higher-level cache to maintain performance monitoring capabilities without storing duplicate data, thereby reducing chip space while preserving performance benefits.
Solution Approach 2:
The tag array and selector array serve multiple functions: they track data presence, enable performance monitoring, and support hit/miss detection across multiple cores. This multi-functionality allows the cache structure to maintain performance benefits without requiring duplicate data storage, resolving the contradiction between performance and chip space.
2Speed
If inclusive multi-level cache structures are used, then data access performance may be improved when lower-level cache data is invalid, but power consumption increases
Solution Approach 1:
The patent removes the data storage component from the higher-level cache, keeping only the metadata structures (tag array and selector array). This extraction eliminates the power consumption associated with maintaining duplicate data while preserving the performance monitoring and hit/miss detection capabilities that improve data access performance.
Solution Approach 2:
The patent changes the state of the higher-level cache from storing actual data to storing only metadata (tags and selectors). This parameter change from data storage to metadata storage significantly reduces power consumption while maintaining the ability to detect cache hits and misses, thereby preserving performance benefits.
3Adaptability or versatility
If duplicate data is stored in higher-level cache, then data availability for other processors is improved, but chip space and power consumption increase
Solution Approach 1:
The patent introduces the selector array as an intermediary structure that tracks data presence without storing duplicate data. This intermediary enables data availability for multiple processors by providing metadata about data location and validity, resolving the contradiction between data availability and chip space requirements.
Solution Approach 2:
Instead of copying actual data to the higher-level cache, the patent copies only the metadata (tag array and selector array) that describes the data. This metadata copying provides data availability information to multiple processors without the chip space overhead of duplicating the actual data content.
Data Source
AI summary
A multi-level cache structure in accordance with one embodiment includes a first cache structure and a second cache structure. The second cache structure is hierarchically above the first cache. The second cache includes a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data. The selector array is configured to specify, for each corresponding tag entry, whether the data array includes the data corresponding to that tag entry.