Dynamic Cache Set Mapping for Wear Distribution

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The extensive use of cache memories on processors leads to uneven wear on certain memory cells due to 'hot' sets, causing decreased lifetime as a result of frequent access, which traditional cache configurations fail to address effectively.

Innovation Solution

Implementing a dynamic set-associative mapping method where cache memory is divided into groups, with only one group assigned at a time, allowing for adjustable set configurations in the assigned group to distribute access evenly and prevent high cycling of memory cells, thereby extending the cache memory's lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional cache configurations are used, then processing performance is improved through memory access locality, but uneven wear on memory cells occurs due to hot sets causing decreased lifetime

Engineering Contradiction:
Improveprocessing performanceVSAvoidcache memory lifetime
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic set-associative mapping where the cache memory configuration changes over time. The cache is divided into multiple groups of sets, and the mapping between memory addresses and cache sets is dynamically switched between different groups based on a time-varying function. This dynamic reconfiguration prevents any single group of sets from being continuously accessed, thereby distributing wear evenly across all memory cells while maintaining high processing performance through temporal locality exploitation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If cache memory capacity is increased to sustain bandwidth demand, then processing performance improves, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvememory bandwidthVSAvoidcache memory structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the cache memory into multiple independent groups of sets. Each group can be independently configured and accessed. This segmentation allows the large cache memory capacity to be organized into smaller, manageable units that can be dynamically switched between. The segmentation approach maintains high memory bandwidth by ensuring that frequently accessed data remains in accessible groups while simplifying the control logic compared to fully associative mappings.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic switching between different groups of cache sets based on a time-varying function. The mapping configuration changes periodically, rotating which group of sets is actively mapped to a given memory address space. This periodic action distributes access patterns evenly across all groups over time, preventing any single group from experiencing excessive wear while maintaining efficient access patterns for sustained memory bandwidth.

Inventive Principle:
Principle #19Periodic action

3Reliability

If dynamic set-associative mapping is implemented to distribute access evenly, then memory cell lifetime is extended, but address mapping complexity increases

Engineering Contradiction:
Improvememory cell enduranceVSAvoidaddress mapping mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the mapping parameter (which group of sets is active) as a function of time and memory address. The specific group selected for mapping varies based on these parameters, creating a dynamic mapping scheme that distributes access evenly across all groups. This parameter-based approach extends memory cell lifetime by preventing hot sets while keeping the mapping mechanism relatively simple through systematic parameter variation rather than complex arbitration logic.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11567875B2Integrated circuit and address mapping method for cache memory
Publication Date: 2023.01.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11567875B2 patent drawing
  • US11567875B2 patent drawing
  • US11567875B2 patent drawing

AI summary

An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups and an address decoder. The groups are assigned in rotation for a plurality of time periods. Each group is assigned in a corresponding single one of the time periods. The address decoder is configured to obtain a set address according to an access address and provide a physical address according to the set address. When the access address corresponds to a first group, the physical address is different from the set address. When the access address corresponds to the groups other than the first group, the physical address is the same as the set address. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups assigned in the time periods other than the first time period.