Selective Cache Set Powering via Content Addressable Memory
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Solution Overview
Problem
Multi-set associative caches in processors consume excessive power due to simultaneous access of all cache sets, even when only one set contains the desired data, leading to increased power wastage and reduced performance throughput per watt.
Innovation Solution
Implementing a content addressable memory (CAM) to selectively power up only the cache set containing the required instruction or data by tracking recent cache line references, thereby reducing unnecessary power consumption and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-set associative cache is configured to reduce cache misses, then cache performance is improved, but power consumption increases due to simultaneous access of all cache sets
Solution Approach 1:
The cache is segmented into multiple independent sets, each capable of being accessed or powered down independently. The system tracks recently accessed cache lines and segments the power-up operation to only activate the specific cache set containing the required data, rather than powering up all sets simultaneously. This segmentation allows the system to maintain multi-set associativity for performance while reducing power consumption by isolating active cache sets.
2Speed
If all cache sets are accessed in parallel to reduce access latency, then cache speed is improved, but power wastage increases due to accessing sets not containing desired data
Solution Approach 1:
The system performs preliminary tracking of recently accessed cache lines in a separate tracking structure before actual cache access occurs. By maintaining this preliminary information about which cache sets are likely to be accessed, the system can pre-identify the specific cache set containing desired data and power up only that set, avoiding the need to access all sets in parallel and thereby reducing power wastage while maintaining fast access.
3Productivity
If more processing cores are placed on a chip to increase throughput, then performance throughput is improved, but power consumption per watt decreases
Solution Approach 1:
Each processing core has its own associated cache sets that it frequently accesses. The system applies local quality by tracking and powering up only the cache sets locally relevant to each core's current execution needs, rather than uniformly powering up all cache sets for all cores. This localized approach ensures that each core gets the cache performance it needs while minimizing the total power consumption across the multi-core system.
Data Source
AI summary
Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.