Two-Level Cache Shadow Tag Updates for DMA Coherence
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Solution Overview
Problem
In digital data processors with a two-level memory subsystem, maintaining coherence between the central processing unit (CPU) and direct memory access (DMA) units leads to increased traffic and stalls due to the need for frequent updates of shadow tags in the level two controller, which are not necessary for all level one data cache updates.
Innovation Solution
Implementing a shadow copy of the level one data cache tag memory in the level two controller to track the status of level one data cache lines, updating shadow tags only on a subset of updates, thereby reducing unnecessary traffic and stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow tags are updated on all level one data cache updates, then cache coherence is maintained, but extra traffic and CPU stalls increase
Solution Approach 1:
The patent applies partial action by updating shadow tags only for a subset of level one cache updates - specifically only when the cache line is allocated to level two directly addressable memory. Updates for external memory lines are omitted, reducing unnecessary traffic while maintaining coherence for the critical subset of memory operations that require it.
2Loss of information
If shadow tags are updated on all level one data cache updates, then coherence tracking is complete, but interface traffic increases
Solution Approach 1:
The patent applies local quality by differentiating the update behavior based on the target memory location. Shadow tags are updated with full coherence tracking for level two directly addressable memory lines, while updates for external memory lines are suppressed. This localized differentiation reduces overall interface traffic while maintaining tracking accuracy where it matters most for DMA coherence.
3Reliability
If shadow tags are updated on all level one data cache updates, then coherence is maintained, but CPU stalls increase
Solution Approach 1:
The patent reduces CPU stalls by applying partial action - updating shadow tags only when necessary for level two directly addressable memory coherence rather than on every level one cache update. This selective approach minimizes the frequency of update operations that could cause CPU stalls while maintaining coherence for the critical subset of memory operations.
Data Source
AI summary
A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.