Cache Slot Aware IO Distribution for Storage Nodes

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Solution Overview

Problem

Current data storage systems face inefficiencies in managing sequential IO operations due to cache-slot unawareness, leading to increased IO processing times and response delays, as host systems lack knowledge of cache slot locations and sizes, resulting in suboptimal distribution of IO operations across storage processing nodes.

Innovation Solution

Implementing a cache-slot aware (CA) distribution scheme within the host system to allocate and manage IO operations based on predefined cache slot boundaries, allowing for efficient allocation and prefetching of data within the same processing node, thereby reducing inter-node communications and response times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If host systems distribute IO operations without cache slot awareness, then IO operations can be distributed across multiple processing nodes, but IO processing times increase and response delays occur due to suboptimal distribution

Engineering Contradiction:
ImproveIO processing throughputVSAvoidIO processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The storage system divides the shared cache into multiple cache slots distributed across different processing nodes. The host system is provided with cache slot location information, enabling it to segment IO operations and distribute them to specific processing nodes based on where the corresponding cache slots are located, thereby reducing inter-node communications and improving IO processing efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by providing the host system with cache slot location information before IO operations are executed. This allows the host system to pre-determine the distribution of IO operations across processing nodes based on cache slot locations, avoiding the need for runtime decisions and reducing IO processing delays

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If sequential IO operations are distributed without cache slot awareness, then load can be distributed across nodes, but inter-node communications increase and response times worsen

Engineering Contradiction:
ImproveIO distribution flexibilityVSAvoidInter-node communication overhead
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The shared cache is segmented into multiple cache slots that are distributed across different processing nodes. By providing cache slot location information to the host system, sequential IO operations can be segmented and directed to specific processing nodes where their corresponding cache slots are located, reducing inter-node communications while maintaining load distribution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements local quality by associating specific cache slots with specific processing nodes and providing location information to the host system. This enables sequential IO operations to be handled locally at the processing node where the cache slot is located, minimizing the need for inter-node communications and improving response times

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11200169B2Cache management for sequential IO operations
Publication Date: 2021.12.14 EMC IP HLDG CO LLC
  • US11200169B2 patent drawing
  • US11200169B2 patent drawing
  • US11200169B2 patent drawing

AI summary

A processing node of a storage system may determine that a host system is implementing a cache-slot aware, round-robin IO distribution algorithm (CA-RR). The processing node may be configured to determine when a sufficient number of sequential IOs will be received to consume a cache slot of the a processing node. If the processing node knows that the host system is implementing CA-RR, then, in response to determining the sufficient number, the processing node may send a communication informing the next processing node about the sequential cache slot hit. If the sequential IO operation(s) are read operation(s), the next processing node may prefetch at least a cache-slot worth of next consecutive data portions. If the sequential IO operation(s) are write operation(s), then the next processing node may request allocation of one or more local cache slots for the forthcoming sequential write operations.