Cache Snoop Limiting for Processor Stall Reduction
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Solution Overview
Problem
In multiple master data processing systems, frequent snoop requests can lead to processor performance issues due to pending snoop requests blocking cache access, causing stalls that negatively impact processor performance.
Innovation Solution
Implementing a cache coherency manager that balances access demands by prioritizing processor requests over snoop requests and limiting snoop requests when a processor has been stalled beyond a threshold, allowing greater cache access through a snoop control interface and arbiter system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If snoop requests are frequently issued to maintain memory coherency, then memory coherency is maintained, but processor performance deteriorates due to cache access blocking
Solution Approach 1:
The patent implements dynamic arbitration that adjusts snoop request handling based on processor stall conditions. When the processor is not stalled, snoop requests are processed normally to maintain coherency. When the processor becomes stalled beyond a threshold, the arbitration dynamically shifts to limit snoop requests, allowing processor access to proceed. This dynamic adaptation resolves the contradiction by making snoop request handling conditional rather than static.
Solution Approach 2:
The system changes the parameter of snoop request priority based on processor stall state. Normally, snoop requests have high priority to ensure coherency. However, when processor stall exceeds a threshold, the priority parameter changes and processor requests are granted preferential treatment. This parameter change allows the system to switch between coherency-maintenance mode and performance-optimization mode.
2Reliability
If snoop requests are prioritized over processor requests, then memory coherency is maintained, but processor access to cache is blocked causing stalls
Solution Approach 1:
The patent applies preliminary anti-action by monitoring processor stall conditions and taking preventive action before excessive stalls occur. The arbitration logic detects when processor requests are being blocked by snoop requests and preemptively limits further snoop requests once a threshold is reached. This prevents the accumulation of excessive stall time while still maintaining coherency during normal operation.
Solution Approach 2:
The system implements feedback by continuously monitoring the stall state of the processor and using this information to adjust snoop request arbitration. The arbitration logic receives feedback about processor stall conditions and dynamically adjusts its behavior - allowing snoop requests when stalls are minimal, but limiting them when stalls exceed the threshold. This closed-loop control resolves the contradiction by making arbitration responsive to actual system conditions.
Data Source
AI summary
In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if the first processing circuitry is prevented from accessing the cache for more than a threshold amount of time. A signal is generated to indicate when the first processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.