Cache Snoop Logic Referee Mode for Coherence Protection
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Solution Overview
Problem
In multiprocessor systems, flush and clean operations face delays due to the creation of new cache copies of target cache lines, leading to repeated retries and incomplete coherence invalidation, which can be exacerbated by ongoing creation of new HPC copies during the processing of these operations.
Innovation Solution
A cache memory with snoop logic that determines coherence ownership and enters a referee mode to protect the target cache line from competing accesses, ensuring no other cache can obtain coherence ownership until the second flush/clean operation is successfully completed, thereby preventing new copies from being created and eliminating sources of delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flush/clean operations are broadcast on the system interconnect, then coherence protection is provided, but delays occur due to repeated retries when new HPC copies are created during processing
Solution Approach 1:
The patent applies preliminary action by having the initiating coherence participant re-acquire coherence ownership before the target cache line processing is complete. This preemptive measure prevents new HPC copies from being created during the processing window, eliminating the need for repeated retries and reducing operation delay while maintaining coherence protection.
2Reliability
If the cache holding the target cache line processes flush/clean operations, then coherence state is updated, but new HPC copies may be created during processing causing incomplete invalidation
Solution Approach 1:
The patent implements feedback by having the initiating coherence participant monitor the processing status of the target cache line and re-acquire coherence ownership when processing is complete. This feedback mechanism ensures that any new HPC copies created during processing are detected and invalidated, maintaining coherence state consistency while enabling faster operation completion through proactive ownership re-acquisition.
Data Source
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AI summary
A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.