Cache Snoop Logic Referee Mode for Flush Operations
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Solution Overview
Problem
In multiprocessor computer systems, flush and clean operations face delays due to the creation of new cache copies of target cache lines, leading to repeated retries and incomplete coherence invalidation, which can be exacerbated by ongoing creation of new HPC copies.
Innovation Solution
A cache memory system with snoop logic that enters a referee mode to protect the target cache line, extending a protection window to prevent competing accesses and ensure successful completion of flush or clean operations by preventing new copies from being created until the operation is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flush or clean operations are broadcast on the system interconnect in a conventional snoop-based coherence protocol, then the operations can be received by all coherence participants, but the operations experience delays due to repeated retries when new HPC copies are created during processing
Solution Approach 1:
The patent applies preliminary action by having the cache that holds the target cache line in HPC state preemptively prevent the creation of new copies before the flush/clean operation completes. This is achieved by setting a protection bit or entering a referee mode that blocks other caches from acquiring HPC state for the target address, ensuring no new copies are created during the operation's processing window.
Solution Approach 2:
The patent introduces an intermediary mechanism (protection bit/referee mode) that mediates between the flush/clean operation and other coherence participants. This intermediary state acts as a gatekeeper, allowing the initiating coherence participant to complete its operation without interference from new HPC copy creations, while still maintaining the overall coherence protocol's functionality.
2Productivity
If the cache holding the target cache line in HPC state processes the flush or clean operation, then the operation can be completed, but other coherence participants cannot create new copies during this time, causing delays
Solution Approach 1:
The patent applies preliminary anti-action by preemptively preventing the harmful effect (creation of new HPC copies) before it can occur. By setting the protection bit or entering referee mode, the system blocks other coherence participants from creating new copies that would otherwise cause retries and delays, thus anti-acting against the problem before it manifests.
3Adaptability or versatility
If multiple processor cores access the same cache line concurrently, then system parallelism is maintained, but coherence protection is compromised when flush/clean operations are interrupted by new HPC copy creations
Solution Approach 1:
The patent maintains concurrent access capability while ensuring coherence by applying preliminary action. The protection bit/referee mode is set in advance to prevent new HPC copies during the critical window when flush/clean operations are processing, allowing other cores to continue accessing different cache lines or shared read-only lines without compromising the integrity of the operation in progress.
Data Source
AI summary
A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush/clean memory access operation of one of a plurality of processor cores that specifies a target address, services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores such that no other coherence participant is permitted to assume coherence ownership of the memory block.