Cache Protection Against Spectre via Permission Checks
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Solution Overview
Problem
Current cache systems are vulnerable to side-channel attacks like Spectre and Meltdown due to speculative execution and lack of timely access permission checks, which can lead to information leakage and security breaches.
Innovation Solution
Implementing a system where access permissions for cachelines are checked at the time of instruction issuance and re-checked at commit time, using extended TLB and CLB entries with additional fields for access permissions and random index values to prevent unauthorized cache state changes and speculative data exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If access permission checks are performed only at commit time, then processing speed is maintained, but security against side-channel attacks deteriorates
Solution Approach 1:
The patent performs access permission checks at instruction issuance time (before execution) in addition to commit time checks. This preliminary action at the issue stage prevents speculative execution of unauthorized instructions, thereby securing the cache against side-channel attacks while maintaining processing throughput by enabling early validation.
2Reliability
If access permission checks are performed at instruction issuance time, then security is improved, but processing speed deteriorates
Solution Approach 1:
The patent introduces a buffer structure that stores access permissions for cachelines. This intermediary buffer allows the system to quickly retrieve pre-computed access permissions during instruction issuance without performing full permission validation, thereby maintaining security while minimizing the performance overhead of frequent checks.
3Productivity
If speculative execution is allowed without re-determination, then processing efficiency is improved, but security deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where access permissions are re-determined at commit time based on the current state of access permission buffers. This feedback loop ensures that even instructions that passed initial permission checks can be validated against updated permissions, preventing security bypasses while allowing speculative execution to proceed efficiently when permissions remain valid.
Data Source
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AI summary
Caches may be vulnerable to side-channel attacks, such as Spectre and Meltdown, that involve speculative execution of instructions, revealing information about a cache that the attacker is not permitted to access. Access permission may be stored in the cache, such as in an entry of a cache table or in the region information for a cache table. Optionally, the access permission may be re-checked if the access permission changes while a memory instruction is pending. Optionally, a random index value may be stored in a cache and used, at least in part, to identify a memory location of a cacheline. Optionally, cachelines that are involved in speculative loads for memory instructions may be marked as speculative. On condition of resolving the speculative load as non-speculative, the cacheline may be marked as non-speculative; and on condition of resolving the speculative load as mis-speculated, the cacheline may be removed from the cache.