Lower Level Cache Speculative Memory Move for Register Pressure
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Solution Overview
Problem
In RISC processor architectures, memory moves consume scarce architected registers, leading to inefficiencies and decreased performance due to the need for load-store instruction pairs that occupy registers for the duration of memory accesses, limiting the availability of these resources for other instructions.
Innovation Solution
Implementing copy and paste functionality, where a lower level cache receives copy and paste requests, and enforces memory access ordering through barrier requests, allowing speculative issuance of memory access requests to alleviate register pressure and improve throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If load-store instruction pairs are used to perform memory moves in RISC architecture, then memory data can be transferred between system memory locations, but architected registers are occupied for the duration of memory accesses, reducing register availability for other instructions
Solution Approach 1:
The memory move operation is segmented into multiple independent load and store instructions that can be executed in parallel with other instructions. Each load instruction loads a portion of the data set to a register, and each store instruction stores from a register to a memory location, allowing fine-grained parallel execution and reducing register occupation time.
Solution Approach 2:
The system dynamically manages register allocation by implementing a register pool that can be dynamically allocated and released. Registers are allocated on-demand for memory move operations and released back to the pool when no longer needed, enabling flexible register usage and improving overall processor throughput.
2Quantity of substance
If multiple load-store instruction pairs are executed sequentially to move large data sets, then complete data transfer is achieved, but register availability is severely limited during the entire operation duration
Solution Approach 1:
Large data set transfers are segmented into multiple smaller load-store instruction pairs, each operating on a portion of the data. This segmentation allows different segments to be processed in parallel or overlapped with other operations, reducing the total time registers remain occupied and improving register utilization efficiency.
Solution Approach 2:
The register pool mechanism ensures continuous useful action by immediately recycling registers back to the pool after use. This eliminates idle time for registers and maintains continuous processor throughput, as registers are continuously available for new operations rather than remaining occupied or idle.
3Productivity
If the number of architected registers is increased to handle memory moves, then register availability improves, but the complexity and resource requirements of the processor increase
Solution Approach 1:
A register pool acts as an intermediary between the limited architected registers and the memory move operations. This pool of temporary registers provides additional storage capacity without requiring permanent expansion of the architected register file, thereby improving register availability while avoiding increased processor structural complexity.
Solution Approach 2:
The system changes the parameter of register availability dynamically through the register pool mechanism rather than statically increasing the number of architected registers. This allows the effective number of available registers to increase during memory move operations without permanently increasing the processor's register file size or complexity.
Data Source
AI summary
In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. Prior to completion of processing of the barrier request by the lower level cache, the lower level cache speculatively issues a request on the interconnect fabric to obtain a copy of a data granule specified by a memory access request among the pluralities of requests that follows the barrier request in program order.