Cache-Based Stack Execution for Fast System Wake-Up
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Solution Overview
Problem
Executing memory reference code that utilizes a stack during system wake-up from a reduced power operational mode is hindered by the unavailability of main memory, leading to significant delays due to reliance on slow ROM access, as the memory controller has not yet been initialized.
Innovation Solution
The memory reference code is executed partially or wholly from the cache, with the stack also implemented in the cache, allowing for efficient use of the processor's cache as a stack and enabling faster system recovery by avoiding cache eviction and utilizing a small portion of RAM as stack RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory reference code is executed from ROM directly to processor pipelines, then the code can be executed without cache eviction issues, but the execution speed is slow contributing significantly to wake-up time
Solution Approach 1:
The patent introduces the processor cache as an intermediary between ROM and processor pipelines. The memory reference code is first loaded from ROM into the processor cache, which then serves as a fast intermediate storage that the processor can access rapidly without the slowness of direct ROM access, thereby resolving the speed bottleneck while maintaining execution reliability
Solution Approach 2:
The patent applies preliminary action by pre-loading the memory reference code from ROM into the processor cache before actual execution begins. This advance preparation ensures that when the processor needs to execute the code, it can do so from the faster cache memory rather than repeatedly accessing the slower ROM, thus improving execution speed without sacrificing reliability
2Speed
If processor cache is used as stack, then stack operations are fast, but the memory reference code may inadvertently evict the stack from cache
Solution Approach 1:
The patent segments the processor cache into distinct functional regions: one portion dedicated to storing the stack data and another portion for executing memory reference code. This segmentation ensures that stack data and code instructions occupy separate cache spaces, preventing code execution from inadvertently evicting stack data while still allowing both operations to proceed at high speed from cache memory
3Reliability
If main memory is used as stack during memory reference code execution, then stack operations are reliable, but main memory is unavailable as memory controller is not yet initialized
Solution Approach 1:
The patent makes the processor cache multi-functional by using it simultaneously as both the execution environment for memory reference code and as the stack storage location. This eliminates the need for main memory initialization before stack operations can begin, as the cache provides both code execution and stack functionality independently of the memory controller's initialization state
Data Source
AI summary
A method and system of executing stack-based memory reference code. At least some of the illustrated embodiments are methods comprising waking a computer system from a reduced power operational state in which a memory controller loses at least some configuration information, executing memory reference code that utilizes a stack (wherein the memory reference code configures the main memory controller), and passing control of the computer system to an operating system. The time between executing a first instruction after waking the computer system and passing control to the operating system takes less than 200 milliseconds.