Cache Memory Controller Supplemental Write Command

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Solution Overview

Problem

Lossless compression in cache systems leads to overfetching of data from main memory due to unused holes in cache lines, resulting in diminished bandwidth benefits and unnecessary power consumption.

Innovation Solution

Implementing a supplemental write command that fills unfilled portions of cache lines with constant or patterned data values, reducing the need for retrieving irrelevant data from main memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If lossless compression is used to reduce data size, then bandwidth efficiency is improved, but overfetching of irrelevant data occurs due to unused holes in cache lines

Engineering Contradiction:
Improvedata sizeVSAvoidirrelevant data
Core Design Contradiction:
Quantity of substanceVSLoss of substance

Solution Approach 1:

The system performs preliminary action by writing supplemental data to fill the holes in cache lines during the write operation, before the read operation occurs. This ensures that when data is later read from the cache, the entire cache line contains valid data, eliminating the need to overfetch irrelevant data from main memory.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Supplemental data acts as an intermediary substance that fills the gaps between compressed data blocks in cache lines. This intermediary data prevents the propagation of irrelevant data from main memory to cache, resolving the contradiction between compression efficiency and data validity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If cache lines are filled with compressed data, then bandwidth compression benefits are achieved, but power consumption increases due to fetching and writing unnecessary data

Engineering Contradiction:
Improvedata compression ratioVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary action by pre-filling cache line holes with supplemental data during write operations. This eliminates the need for subsequent read operations to fetch and write irrelevant data from main memory, directly reducing power consumption while maintaining compression benefits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system converts the harmful effect of unused holes in cache lines (which cause overfetching and power waste) into a benefit by systematically filling these holes with supplemental data. This transforms the previously harmful gap-filling requirement into an opportunity to eliminate future power-wasting operations.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of substance

If supplemental data is written to fill cache line holes, then overfetching is eliminated, but cache memory usage increases

Engineering Contradiction:
Improveirrelevant dataVSAvoidcache memory usage
Core Design Contradiction:
Loss of substanceVSQuantity of substance

Solution Approach 1:

The system extracts only the necessary compressed data from main memory and leaves the hole-filling task to be performed by writing supplemental data locally in the cache. This extraction approach reduces the amount of data transferred from main memory while achieving the same goal of filling cache line holes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system changes the parameter of cache line composition by introducing supplemental data with specific characteristics (valid but not necessarily useful data). This parameter change allows the cache to maintain full lines without requiring all data to be equally useful, resolving the contradiction between complete cache lines and minimal memory usage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9612971B2Supplemental write cache command for bandwidth compression
Publication Date: 2017.04.04 QUALCOMM INC
  • US9612971B2 patent drawing
  • US9612971B2 patent drawing
  • US9612971B2 patent drawing

AI summary

Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.