Cache Swizzle with Inline Transposition for SIMD Efficiency
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Solution Overview
Problem
Existing data processing systems face significant performance overhead in arranging data into formats suitable for SIMD execution units, particularly when data is stored in array of structures (AOS) format and needs to be processed in structure of arrays (SOA) format, leading to inefficient cache bandwidth usage and suboptimal processing capabilities.
Innovation Solution
The solution involves selectively swizzling data in cache memory based on swizzle-related page attributes stored in memory address translation data structures like ERAT or TLB, optimizing data formatting for efficient processing by accessing and rearranging data prior to storage in cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in array of structures (AOS) format in memory and loaded directly into cache, then cache bandwidth is conserved, but SIMD execution units cannot efficiently process the data due to mismatched format requirements
Solution Approach 1:
The patent performs data swizzling (rearrangement from AOS to SOA format) in advance during the cache load operation itself, rather than loading data first and then rearranging. The load logic detects the swizzle attribute and directly reorganizes data into the desired format while loading into cache, eliminating subsequent format conversion operations and reducing cache bandwidth consumption.
Solution Approach 2:
The patent introduces a swizzle attribute stored in page table entries that acts as an intermediary control mechanism. This attribute communicates the desired data format requirement from the SIMD execution unit to the cache load logic, enabling the load operation to automatically perform appropriate data rearrangement without requiring explicit software intervention or additional conversion instructions.
2Productivity
If data is rearranged in the vector register file after loading, then correct format is achieved for SIMD processing, but many wasteful instructions are consumed
Solution Approach 1:
The patent performs the data rearrangement operation preliminarily during the cache load phase, before data enters the vector register file. The load logic uses the swizzle attribute to determine whether to rearrange data, and if needed, performs the transformation as part of the load operation itself, eliminating the need for separate rearrangement instructions in the vector register file.
Solution Approach 2:
The patent extracts the data rearrangement functionality from the vector register file operations and moves it to the cache load logic. By separating this formatting function from the processing pipeline and integrating it into the memory subsystem, the patent eliminates wasteful instructions in the register file while maintaining correct data formatting for SIMD operations.
3Productivity
If every load makes multiple accesses into data cache to retrieve and rearrange data, then correct format is achieved, but cache bandwidth is heavily consumed
Solution Approach 1:
The patent performs data swizzling preliminarily during the single cache access operation. The load logic detects the swizzle attribute and rearranges data on-the-fly during the load transaction, so that data is retrieved from memory in the correct format and stored directly into the cache in the desired arrangement, eliminating the need for multiple subsequent cache accesses.
Solution Approach 2:
The patent merges the data rearrangement operation with the cache load operation into a single unified process. Instead of performing load and then rearrange as separate operations requiring multiple cache accesses, the swizzle function is integrated into the load logic, allowing both operations to complete in one cache transaction and reducing overall cache access complexity.
Data Source
AI summary
A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.