Cache-Symmetric Tile Enumeration for Volume Rendering
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Solution Overview
Problem
Existing volume rendering methods face limitations in cache reuse across tiles, leading to suboptimal performance due to inefficient memory access strategies, particularly in shared memory systems with multiple processors, where synchronization overhead and lock contention hinder efficient workload distribution.
Innovation Solution
A dynamic load balancing method that decomposes the image into regions, assigns sockets to these regions, and uses a cache-symmetric tile enumeration scheme to minimize split operations and maximize cache locality, allowing for non-blocking or nearly lock-free operation by utilizing atomic instructions and adaptive workload distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic load balancing with tile decomposition is used, then workload distribution is improved, but synchronization overhead and lock contention increase
Solution Approach 1:
The system uses atomic instructions that automatically handle synchronization without requiring external lock management. Each processor independently performs compare-and-swap operations on tile state variables, eliminating the need for centralized lock coordination and reducing synchronization overhead while maintaining effective workload distribution
Solution Approach 2:
The patent replaces traditional mechanical lock-based synchronization mechanisms with atomic instruction-based coordination. Instead of using locks that require acquisition and release operations, the system uses hardware-supported atomic compare-and-swap instructions that provide lock-free synchronization, reducing both overhead and contention
2Power
If image space decomposition into tiles is applied, then parallel processing capability is improved, but cache reuse efficiency deteriorates
Solution Approach 1:
The system dynamically adjusts tile processing order based on cache state and processor socket assignments. By using atomic operations to track tile completion status and implementing adaptive tile assignment strategies, the system optimizes cache utilization while maintaining parallel processing efficiency across multiple sockets
Solution Approach 2:
The patent introduces a new dimension of optimization by considering processor socket assignments and cache hierarchy levels in tile enumeration. Instead of simple linear tile ordering, the system uses multi-dimensional tile indexing that accounts for socket-specific cache characteristics, enabling better cache reuse across the distributed cache hierarchy while preserving parallel processing capability
Data Source
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AI summary
Present invention relates to a method, system and product for volume rendering of medical images on a shared memory system (10) implemented on a multi-socket mainboard with multiple multi-core processors (P) and multiple last level caches (LLC), wherein each processor (P) may calculate instructions of at least one thread in parallel, wherein cores (C) that share a cache (12) are united in a socket (S). The method comprises: - Decomposing the image space (MR) to be used for rendering in regions (Re), wherein each region (Re) comprises a plurality of tiles (T); - Assigning two sockets (S) to each of the decomposed regions (Re) for the purpose of rendering; - Determining a tile enumeration scheme for a region (Re) wherein the tile enumeration scheme comprises a regular and a corresponding reverse indexing for tile calculation by the two assigned sockets (S); - Rendering all tiles (T) of the plurality of tiles (T) within a region (Re) according to the determined tile enumeration scheme on the assigned two sockets (S) until the respective region (Re) is finished; - If a region (Re) is finished: Assigning the two sockets (S) to another region (Re); - If no region (Re) is left: Splitting an existing region of un-rendered tiles into sub-regions according to a splitting scheme and applying the steps recursively for the sub-regions.