On-Chip Cache Synchronization for Image Sensor Data Chaining
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Solution Overview
Problem
Current computing systems face challenges in reducing latency and power consumption during data processing, particularly when handling image data, due to inefficiencies in memory access and data transfer between producer and consumer resources, which can lead to increased processor utilization and frame delays.
Innovation Solution
A computing scheme that utilizes a system-level cache as an elastic buffer for sub-frame data sharing, employing tokens and data flow characteristics to synchronize and manage data transfers between producer and consumer resources, minimizing the data footprint and avoiding unnecessary write operations to DRAM, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional memory access methods are used for data transfer between producer and consumer resources, then data can be transferred, but latency increases and power consumption increases
Solution Approach 1:
The patent introduces a system-level cache as an intermediary buffer between the producer resource (image sensor) and consumer resource (processor). This cache acts as a mediator that decouples the producer-consumer relationship, allowing data to be stored locally without immediate transfer to DRAM, thereby reducing latency and avoiding unnecessary DRAM access operations that consume additional power.
Solution Approach 2:
The patent segments the data transfer process into two distinct paths: a fast on-chip data path for transferring sub-frames of image data to the cache, and a separate token path for synchronization signals. This segmentation allows independent optimization of data transfer speed and synchronization, reducing overall latency while minimizing power-consuming DRAM transactions.
2Productivity
If data is transferred directly to DRAM for processing, then data availability is ensured, but processor utilization increases and frame delays occur
Solution Approach 1:
The system performs preliminary action by pre-fetching and storing sub-frames of image data in the on-chip cache before they are needed for processing. The producer resource continuously feeds data to the cache, and the processor can then access pre-loaded data without waiting for sequential DRAM transfers, thereby reducing frame delays and improving processor utilization efficiency.
Solution Approach 2:
The patent implements dynamic memory allocation where the system-level cache allocates a variable amount of memory based on the quantity of active producer-consumer pairs. This dynamic allocation allows the cache to adapt to varying processing demands, ensuring optimal buffer space utilization and preventing frame delays during high-workload periods while maintaining efficient processor operation.
3Device complexity
If tokens are transferred using the same data path as frame data, then simplicity is maintained, but data footprint increases and bandwidth is consumed
Solution Approach 1:
The patent segments the communication infrastructure into two separate paths: a first data path dedicated to transferring frame data (sub-frames of image pixel data) to the cache, and a second data path dedicated to transferring synchronization tokens. This segmentation reduces the data footprint by avoiding redundant token transmissions over the high-bandwidth data path, while the separation is implemented in a way that maintains overall system simplicity.
Solution Approach 2:
The patent extracts the token transfer function from the main data transfer path. By separating tokens into their own dedicated path, the system eliminates unnecessary bandwidth consumption and reduces the effective data footprint, while the extraction is designed to be transparent to the overall system architecture, maintaining simplicity through modular design.
4Productivity
If elastic memory buffer is used for sub-frame data, then data sharing efficiency improves, but memory management complexity increases
Solution Approach 1:
The patent implements feedback mechanisms through the token system that provides information about data consumption status back to the producer resource. This feedback loop enables automatic adjustment of data transfer timing and buffer allocation, improving data sharing efficiency while the feedback protocol is designed to simplify memory management by automating allocation decisions based on actual usage patterns.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.