Cache System for DRAM-PCM Hybrid Memory
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Solution Overview
Problem
Flash memory and PCM systems face challenges with limited endurance and higher access latency compared to DRAM, necessitating a cache controlling method to manage both DRAM and PCM systems without complex hardware control circuits.
Innovation Solution
A cache system comprising a first cache for storing data status and a second cache for a table with data arranged from highest to lowest access frequency, using hardware to track recent access and software to manage data structure, ensuring that frequently accessed data is prioritized in the DRAM cache and less frequently accessed data is managed accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache system with complex hardware control circuits is used to manage DRAM and PCM systems, then the access latency and performance can be improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts the complex hardware control circuit functionality and replaces it with software-based management in the host processor. The cache status tracking and data placement decisions are moved from hardware to software, simplifying the hardware control circuit while maintaining cache management capabilities through software algorithms that track access patterns and manage data placement between DRAM and PCM.
Solution Approach 2:
The patent substitutes the mechanical/hardware control system with a software-based control mechanism. Instead of using dedicated hardware control circuits to manage cache status and data placement, the system uses software routines executed by the host processor to track access patterns, update cache status, and make data placement decisions, thereby reducing hardware complexity while achieving the same functional goals.
2Productivity
If frequent updates are made to the management data structure in the cache system, then the data placement optimization can be improved, but the runtime costs and execution time increase
Solution Approach 1:
The patent implements periodic updates to the management data structure rather than continuous updates. The cache status is tracked continuously in hardware, but the software-based management data structure is updated only at specific intervals or triggered by specific events (such as cache misses or threshold-based conditions). This periodic update approach maintains data placement optimization while significantly reducing the runtime overhead associated with frequent updates.
Solution Approach 2:
The patent applies partial updates to the management data structure by only updating entries that have changed or meet specific criteria, rather than updating the entire data structure. This selective update approach reduces the computational overhead and execution time while still maintaining the necessary optimization information for data placement decisions.
3Use of energy by moving object
If PCM is used to replace DRAM as main memory, then the power consumption is reduced, but the access latency increases
Solution Approach 1:
The patent applies local quality by creating a heterogeneous memory system where DRAM and PCM serve different functional roles. DRAM is used for frequently accessed data requiring fast access, while PCM is used for less frequently accessed data where lower power consumption is prioritized. The software-based cache management system dynamically assigns data to appropriate memory technologies based on access patterns, thereby optimizing the balance between power consumption and access latency for different data sets.
Solution Approach 2:
The patent introduces a software-based cache management system as an intermediary layer between the CPU and the DRAM-PCM hybrid memory system. This intermediary tracks access patterns, manages cache status, and makes intelligent data placement decisions to keep frequently accessed data in fast DRAM while storing less frequently accessed data in power-efficient PCM, thereby mitigating the access latency issue while maintaining power savings.
Data Source
AI summary
A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.