Cache Tag Array Hard Error Proofing via External Correction
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Solution Overview
Problem
Cache memory systems face issues with 'hard' errors due to physical defects in the cache tag array, leading to endless loops and delays when trying to correct stuck bits, which prevent cache hits and cause processing inefficiencies.
Innovation Solution
The cache controller corrects error-prone cache tag entries and stores the corrected entries externally, allowing for a successful comparison and data retrieval even in the presence of hard errors by replaying the address request with the externally stored corrected entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache controller continuously retries correcting stuck bits in the cache tag array, then error correction attempts are made, but endless loops occur and processing time is wasted
Solution Approach 1:
The system performs preliminary error detection and correction attempts before committing to continuous retry loops. When a stuck bit is detected during error correction, the system proactively switches to using a backup tag array rather than continuously retrying the corrupted entry, thus avoiding endless loops and saving processing time.
Solution Approach 2:
A backup tag array serves as an intermediary solution when the primary tag array contains hard errors. Instead of directly continuing to use the corrupted tag array, the system transitions to the backup tag array which contains valid tag data, thereby mediating between the error state and successful cache operation.
2Reliability
If the cache controller uses error correction codes to detect and correct tag errors, then reliability improves, but device complexity increases due to additional correction logic and storage
Solution Approach 1:
The system creates a backup copy of the tag array that can be used when the primary tag array develops hard errors. This copying approach provides redundancy and reliability without implementing complex real-time error correction logic, as the backup serves as a simple alternative data source when needed.
3Measurement precision
If the cache controller implements comprehensive error detection and correction, then data accuracy improves, but the cache access speed decreases due to additional verification steps
Solution Approach 1:
The system implements partial error correction by using error detection codes to identify potential errors and applying correction only when necessary. Rather than performing comprehensive verification on every cache access, the system uses lightweight parity or ECC checks and only invokes full error correction procedures when errors are detected, thus maintaining speed while ensuring accuracy.
Data Source
AI summary
A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.