Cache Memory Tag Array Segmentation for Power Reduction
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Solution Overview
Problem
Integrated circuits with multiple processing units face high power consumption due to cache memory circuitry, which is not efficiently managed in existing technologies, leading to inefficiencies in power management and performance.
Innovation Solution
A cache memory system that separates data storage into a cache memory and a persistent memory, where the cache memory is placed in a reduced power consumption state while the tag array remains operational, allowing for efficient data retrieval from persistent memory during cache access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the cache memory is placed in a reduced power consumption state, then power consumption is reduced, but data retrieval speed deteriorates
Solution Approach 1:
The cache memory is segmented into two independent parts: the storage array and the tag array. The storage array is placed in a reduced power consumption state while the tag array remains fully operational. This segmentation allows the system to reduce overall power consumption while maintaining the ability to perform tag lookups and retrieve data from external memory when needed.
Solution Approach 2:
Data is pre-copied from the cache storage array to external memory before the cache is placed in the reduced power state. This preliminary action ensures that data is available in external memory and can be retrieved without delay when access is needed, while the cache itself consumes minimal power.
2Speed
If the entire cache memory is kept operational, then data retrieval speed is maintained, but power consumption increases
Solution Approach 1:
The cache memory is divided into the storage array and tag array, allowing independent power management. Only the tag array remains fully operational while the storage array enters low-power mode, reducing overall power consumption while maintaining lookup functionality.
Solution Approach 2:
The cache storage array alternates between full operational mode and reduced power consumption state based on access patterns. When data is accessed, the storage array is activated; when not accessed, it enters low-power mode. This periodic activation maintains data retrieval capability while reducing average power consumption.
3Use of energy by moving object
If the cache memory is completely powered down, then power consumption is minimized, but access latency increases
Solution Approach 1:
The tag array remains fully operational while the storage array is powered down. This segmentation enables fast tag lookups to determine if data exists in the cache, and if so, to retrieve it from external memory, significantly reducing access latency compared to complete power-down.
Solution Approach 2:
Data is pre-transferred to external memory before the cache storage array is powered down. This preliminary action ensures that data is readily available in external memory, allowing quick retrieval without the latency associated with data transfer from a powered-off cache.
Data Source
AI summary
Processors may include cache circuitry that is a significant source of power consumption. A cache is going to be placed into a lower power mode. Based at least in part on this anticipated transition, the contents of the cache data lines are copied into persistent storage. While the cache is in the lower power mode, the tag circuitry is kept operational. When an access request is made to the cache, a relatively fast lookup of the tag in the tag array can be made. The location where the associated cache line is stored in the persistent storage may be determined from the tag data. Upon a tag hit, the system is able to find the contents of the requested cache line in the persistent storage without returning the storage array of the cache to a fully operational state.