Cache Memory Tag Separation Across Memory Arrays
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Solution Overview
Problem
Implementing a cache memory with a large storage capacity results in significant die area consumption by associated tag circuits, which are required for identifying data stored in the cache memory.
Innovation Solution
Storing data and tags in different bank groups of memory cells within cache memory, where data blocks are stored in one bank group and their corresponding tags are stored in a separate bank group, allowing for efficient access and reduced tag circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache memory storage capacity is increased, then data access efficiency is improved, but tag circuit die area consumption increases significantly
Solution Approach 1:
The patent divides the traditional unified cache structure into separate data storage array and tag storage array. This segmentation allows independent optimization of each array, reducing the die area overhead of tag circuits while maintaining large cache capacity. The data array stores actual cache data while the tag array stores only metadata, separating functionality and reducing area consumption.
Solution Approach 2:
The patent transitions from a two-dimensional organization (data and tags in same array) to a three-dimensional structure by adding a separate tag array dimension. This allows tags to be stored in a dedicated array with different access patterns, enabling efficient tag comparison without consuming additional die area proportional to cache size.
2Device complexity
If data and tags are stored in the same memory array, then access simplicity is maintained, but access time efficiency deteriorates
Solution Approach 1:
By segmenting the memory system into separate data and tag arrays, the patent enables parallel access operations. The tag array can be accessed and compared independently from the data array, allowing tag validation to occur without blocking data retrieval, thus reducing overall access time despite increased structural complexity.
Solution Approach 2:
The separate tag array allows preliminary tag comparison to be performed in parallel with data array access. The tag validation can begin immediately without waiting for data array operations, effectively preprocessing the validation step and reducing critical path delay.
Data Source
AI summary
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.