Pseudo Direct Mapped Cache Tag Data Organization
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Solution Overview
Problem
Current computer systems face performance bottlenecks due to high latency in memory access, particularly in cache architectures, as they rely on power-consuming SRAM for last-level caches, while alternative low-cost memory technologies like DRAM and HBM offer high capacity and bandwidth but at the cost of increased latency.
Innovation Solution
Implementing a data processing system with a cache controller that forms a direct or pseudo direct mapped cache architecture, where each memory page includes both data and tag areas, optimizing cache hits by using modulo arithmetic or hashing to locate memory locations, and distributing tags and data across multiple pages to reduce latency and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM-based caches are used for last-level caches, then processing speed and cache performance are improved, but power consumption and circuit area increase
Solution Approach 1:
The patent replaces expensive SRAM-based caches with DRAM-based caches that use cheaper memory cells. DRAM uses capacitors that can be made with simpler transistor structures (1T1C vs 6T in SRAM), reducing power consumption and circuit area while maintaining cache functionality through periodic refresh operations
Solution Approach 2:
The patent changes the fundamental memory cell parameters by transitioning from SRAM's volatile flip-flop-based storage to DRAM's capacitor-based storage. This parameter change enables lower power consumption and reduced circuit area while accepting the need for refresh operations to maintain data integrity
2Quantity of substance
If low-cost memory technologies like DRAM and HBM are used instead of SRAM, then memory capacity and bandwidth are improved, but processing latency increases
Solution Approach 1:
The patent implements a cache controller that pre-charges bit lines and pre-fetches data before actual read operations are needed. By performing preliminary actions such as pre-charging memory bit lines and preparing data in advance, the system reduces the effective access latency when data is actually requested, making DRAM/HBM perform closer to SRAM speeds
Solution Approach 2:
The patent maintains continuous cache operations by implementing overlapping read and write operations, and keeping the cache controller continuously active to manage data flow between DRAM/HBM and the processor. This continuous operation minimizes idle time and reduces effective latency through pipelining
3Adaptability or versatility
If tags and data are stored in separate memory locations, then cache flexibility and management are improved, but access overhead and latency increase
Solution Approach 1:
The patent merges tag storage and data storage into the same DRAM/HBM memory structure, using the same memory array to store both tag information and actual data. This integration eliminates separate access operations for tags and data, reducing access overhead and latency while maintaining cache management flexibility through unified memory addressing
Data Source
AI summary
A data processing system includes a processor and a cache controller coupled to the processor, and adapted to be coupled to a memory. The cache controller uses the memory to form a pseudo direct mapped cache having a plurality of groups of pages. The memory forms a first number of selected pages, including a first page for storing a plurality of sets of tags and a plurality of remaining pages for storing data. Each tag, of the plurality of sets of tags, stores tags for respective entries in a corresponding one of the plurality of remaining pages.