Hierarchical Cache Tag Directory Segmentation for Access Efficiency
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Solution Overview
Problem
Cache access efficiency degrades in arithmetic processing devices with hierarchical caches due to frequent access to the tag directory of the DRAM cache, especially in inclusion schemes where data is evicted from internal caches during write-back operations, leading to performance issues.
Innovation Solution
Incorporating a second cache with a separate tag region that holds information about cache line data, allowing the processor to determine the write-back location without accessing the external cache, thereby reducing the frequency of cache access and maintaining data in internal caches during replacement processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a DRAM cache is coupled to a die including an internal cache to increase cache capacity, then cache capacity is improved, but access efficiency to the tag directory of the DRAM cache degrades due to frequent accesses
Solution Approach 1:
The tag directory is segmented into two parts: a first tag directory stored in the internal cache (first cache) for frequent access, and a second tag directory stored in the DRAM cache (second cache) for capacity. The processor first checks the first tag directory, and only accesses the second tag directory when necessary, reducing the frequency of DRAM cache accesses while maintaining high cache capacity.
2Adaptability or versatility
If data is evicted from internal caches during write-back operations in inclusion schemes, then cache replacement is enabled, but cache access efficiency degrades due to frequent tag directory accesses
Solution Approach 1:
The system performs preliminary action by storing tag directory information in the internal cache (first tag directory) before actual cache operations occur. This allows the processor to quickly determine whether data exists in the internal cache or DRAM cache without frequently accessing the external memory, thereby maintaining cache replacement capability while improving access efficiency.
3Reliability
If the processor determines write-back location by accessing the external cache, then accurate write-back control is achieved, but cache access frequency increases leading to performance degradation
Solution Approach 1:
A copy of the tag directory information is created and stored in the internal cache (first tag directory). This copy contains sufficient information for the processor to determine write-back locations without accessing the external cache. The copy is updated periodically to maintain consistency, thereby reducing cache access frequency while preserving write-back control accuracy.
Data Source
AI summary
An arithmetic processing device includes: an arithmetic circuit that executes an instruction; a first cache which is coupled to the arithmetic circuit and which has a plurality of first entries each including a first tag region and a first data region that holds cache line data; a second tag region; a processor which controls the first cache based on information held in the second tag region; and a second cache which is coupled to the first cache via the processor and which includes a plurality of second entries each of which includes a third tag region and a second data region that holds cache line data. The second tag region includes a first region that holds first information which specifies whether or not the second data region holds cache line data which has the same address as the address of cache line data held in the first data region.