Cache Tag Hashing Across SRAM and DRAM to Cut Tag Size
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Solution Overview
Problem
The size and cost of cache tags in large caches, particularly those using static random access memory (SRAM), pose significant challenges due to high physical silicon cost and power consumption, while existing tag compression techniques are either inefficient in area or require additional implementation space.
Innovation Solution
Implementing a two-stage cache tag lookup system using multiple hash functions, where primary tags are stored in SRAM and secondary tags in DRAM, reducing the number of bits needed in SRAM and allowing for efficient energy and area usage while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If tags are stored in SRAM for fast access, then cache hit latency is reduced, but physical silicon cost and power consumption increase significantly
Solution Approach 1:
The patent segments the tag storage system into two parts: primary tags stored in SRAM for fast access during cache hits, and secondary tags stored in DRAM for comprehensive coverage. This segmentation allows the system to benefit from SRAM speed for frequent operations while using cheaper DRAM for the full tag set, thereby reducing overall power consumption and silicon cost while maintaining fast access performance.
2Speed
If SRAM is used to store all cache tags, then tag access speed is improved, but physical silicon area and cost become prohibitively expensive
Solution Approach 1:
The patent divides tag storage into primary tags in SRAM and secondary tags in DRAM. The primary tags occupy minimal SRAM area while providing fast access, and the secondary tags reside in DRAM which is more area-efficient for large-scale storage. This segmentation resolves the contradiction by allocating tag storage across memory types based on their respective strengths.
Solution Approach 2:
The patent introduces a hierarchical dimension to tag storage, organizing tags across two memory layers (SRAM and DRAM) rather than using a single flat memory structure. This dimensional approach allows the system to optimize for both speed (SRAM layer) and area efficiency (DRAM layer) simultaneously.
3Area of stationary object
If DRAM is used to store all cache tags, then area and cost are reduced, but access latency increases due to slower DRAM speed
Solution Approach 1:
The patent segments tag storage so that frequently accessed primary tags are placed in SRAM for fast access, while less frequently accessed secondary tags are stored in DRAM. This segmentation ensures that the critical path for cache hits remains fast while still benefiting from DRAM's area efficiency for the complete tag set.
4Quantity of substance
If tag compression techniques are applied, then tag size is reduced, but implementation complexity and additional area requirements increase
Solution Approach 1:
The patent segments tags into primary and secondary portions with distinct functions. Primary tags are compressed representations used for fast comparison in SRAM, while secondary tags provide full identification in DRAM. This segmentation achieves tag size reduction without requiring complex compression algorithms, as the segmentation itself provides the compression benefit.
Data Source
AI summary
An example of a system using two-stage, the cache tag is stored in a primary and a secondary tag memories. When requesting data, the system searches the cache to retrieve the data, an operation that involves cache tag lookup. Cache tag lookup is performed by cache management. The cache management receives a cache tag for reading data from the cache memory. The cache management selects a hash function from a group of hash functions and computes a primary lookup tag using the selected hash function and the cache tag. The cache management compares the primary lookup tag to the contents of the primary tag memory to determine if there is a hit. If there is no hit, the cache management selects another hash function and repeats the search in the primary tag memory.