Cache Tag Memory Parallel Arbitration for Load Access Throughput
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Solution Overview
Problem
Conventional microprocessor architectures face challenges in sustaining throughput when handling multiple load accesses to a cache in a single cycle, particularly due to arbitration delays and penalties for unaligned accesses, which result in reduced performance and increased latency.
Innovation Solution
The proposed solution involves a method where a tag memory maintains multiple copies of tags for each entry in the data cache, allowing parallel access arbitration and bypass paths for requests accessing the same cache block, and enabling unaligned accesses to access multiple blocks without splitting, thus avoiding timing penalties and enhancing cache hit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional arbitration schemes are used to determine which request accesses a given tag and data bank, then access conflicts are resolved, but the arbitration time delays access to the tag bank and reduces throughput
Solution Approach 1:
The patent performs tag comparison in advance before arbitration. Multiple tags are compared against the requested address simultaneously, and the results are stored in priority encoders. This preliminary tag comparison eliminates the need for time-consuming arbitration delays, as the system already knows which requests should access which banks before the actual access occurs.
Solution Approach 2:
The patent divides the cache into multiple independent tag banks and data banks. Each bank can be accessed independently, and arbitration is performed on a per-bank basis rather than for the entire cache. This segmentation allows parallel processing of multiple requests and reduces the critical path delay for arbitration.
2Productivity
If multiple load accesses attempt to access the same block in a single cycle, then throughput is increased, but conventional arbitration penalizes all but one access by returning Load Miss
Solution Approach 1:
The patent maintains multiple copies of tags in separate tag banks, with each bank having its own copy of the tag information. When multiple requests access the same block, each request can find its corresponding tag in its assigned tag bank, allowing all requests to receive Load Hit signals simultaneously without penalizing any of them.
Solution Approach 2:
The system performs preliminary tag comparison for all requests before arbitration. The priority encoders store the results of tag comparisons in advance, allowing the system to identify all successful matches before any arbitration occurs. This ensures that all valid requests receive Load Hit signals, maintaining high cache hit rates even when multiple requests access the same block.
3Ease of operation
If unaligned load accesses are split into two components before sending to Level-1 cache, then address alignment is achieved, but the two components cannot be sent at the same time and never result in a Level-1 cache hit
Solution Approach 1:
The patent divides the cache address space into multiple segments, each handled by a separate tag bank. Unaligned accesses can be distributed across different tag banks rather than being split into sequential components. Each tag bank independently handles its portion of the unaligned access, allowing all components to be processed simultaneously in the same cycle.
Solution Approach 2:
The patent introduces a new dimension of parallelism by using multiple independent tag banks that can be accessed simultaneously. Instead of processing unaligned accesses sequentially in a single tag bank, the system distributes them across multiple banks, enabling parallel processing of all components of an unaligned access in the same cycle.
Data Source
AI summary
A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.