Cache Tag Power Gating for Mobile IC Energy Reduction
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Solution Overview
Problem
Integrated circuits in mobile devices face challenges in reducing power consumption, which affects battery life and heat generation, as existing power management techniques are not sufficient to efficiently manage cache coherency and related structures.
Innovation Solution
A computer system implements a cache coherency scheme using a coherence point with a duplicate set of tag structures, powering down caches and corresponding coherence point components when not in use to minimize power consumption through clock and power gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If caches and coherence point structures are continuously powered to maintain cache coherency, then cache coherency reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management by transitioning caches and coherence point structures between powered-on and powered-off states based on validity status. When cache lines are invalidated, the corresponding duplicate tag structures in the coherence point are also powered down, creating a dynamic adaptation to actual operational needs rather than continuous operation.
Solution Approach 2:
The patent applies selective power management to specific portions of the coherence point rather than the entire structure. Only the duplicate tag structures corresponding to invalidated cache lines are powered down, while other portions remain operational. This localized approach maintains cache coherency where needed while reducing power consumption where not required.
2Use of energy by moving object
If caches are powered down to reduce power consumption, then power consumption is reduced, but cache coherency management complexity increases
Solution Approach 1:
The patent combines the power management control logic with the existing cache coherence protocol. The same invalidation signals that trigger cache line invalidation also trigger the powering down of duplicate tag structures in the coherence point. This merging of functions eliminates the need for separate power management control logic, reducing overall system complexity despite the added power states.
3Use of energy by moving object
If duplicate tag structures in coherence point are powered down with caches, then power consumption is reduced, but coherency check time increases upon power up
Solution Approach 1:
The patent performs preliminary reinitialization of duplicate tag structures during cache power-up before full operational use. When a cache is powered back up, its corresponding duplicate tag structures in the coherence point are reinitialized in advance, ensuring they are ready for immediate coherency checks without delaying subsequent operations.
Data Source
AI summary
Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.