Cache Tag RAM Access Reduction via Determination Purpose Flag
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Solution Overview
Problem
The existing cache coherency protocols, such as the MESI protocol, result in unnecessary access to the TAG-RAM during cache misses, leading to reduced processing performance due to the need for multiple accesses to validate cache states, especially in cases where data needs to be written back or invalidated.
Innovation Solution
An information processing apparatus with a determination unit that sets a determination purpose flag based on cache states, reducing the need for TAG-RAM access by invalidating cache blocks without re-checking their states when the flag indicates a non-M state, thereby optimizing cache management during cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the primary cache management unit checks the cache state by accessing TAG-RAM during a cache miss, then data coherency is maintained, but the response time increases due to multiple accesses required
Solution Approach 1:
The patent applies preliminary action by setting the determination purpose flag in advance based on the cache state before the actual data transfer occurs. When the flag indicates a non-M state, the system can skip the TAG-RAM access during the data storage request processing, thus reducing response time while maintaining coherency through the pre-established flag information.
2Reliability
If the primary cache management unit performs protocol check by accessing TAG-RAM for every data storage request, then cache state validation is ensured, but processing performance decreases due to unnecessary accesses
Solution Approach 1:
The patent extracts the essential coherency information into a determination purpose flag that is set in advance. This flag contains the necessary validation information without requiring full TAG-RAM access, thus taking out only the critical coherency check mechanism while eliminating unnecessary protocol verification steps that reduce processing performance.
Solution Approach 2:
Instead of performing complete protocol checks with full TAG-RAM accesses for every data storage request, the patent applies partial action by using the determination purpose flag to perform only the necessary coherency validation. This partial check is sufficient for maintaining data coherency while avoiding excessive TAG-RAM accesses that would degrade processing performance.
3Reliability
If the system performs write back operation for M state cache blocks during cache miss, then data coherency is maintained, but the number of TAG-RAM accesses increases
Solution Approach 1:
The system performs preliminary action by setting the determination purpose flag in advance to indicate whether the cache block is in M state. This pre-established information allows the system to handle write back operations more efficiently by knowing in advance whether they are necessary, thus reducing the overall number of operations required while maintaining data coherency.
Data Source
AI summary
A tag match determination unit determines, in response to an acquisition request for predetermined data, whether predetermined data is present in a primary cache. When the predetermined data is not present in the primary cache, the move-in buffer outputs the acquisition request for the predetermined data to a secondary cache management unit or the storage device and holds determination purpose information based on state information on a predetermined area that stores therein the predetermined data. A storage processing unit determines, when an acquired response from the secondary cache management unit or the storage device is a predetermined type, based on the determination purpose information, whether or not to acquire the state information stored in the primary cache; invalidates the predetermined area when it is determined not to acquire the state information; and stores, in the predetermined area, the predetermined data included in the response.