Two-Phase Cache Tag Lookup for Low-Energy Way Halting
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Solution Overview
Problem
Current way halting techniques in cache memory systems suffer from high energy consumption and area overhead due to duplication of efforts across many ways, and incur delay penalties due to parallel operations and long cycletimes, making them unsuitable for modern designs.
Innovation Solution
Implement a two-phase tag lookup process using a preamble tag memory and one or more prologue tag memories, where the first phase determines a partial hit using preamble bits, and the second phase uses prologue bits to confirm a complete hit or miss, thereby reducing unnecessary accesses and optimizing energy savings and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ways are accessed all at once using an incoming address to find a matching address, then the tag lookup can be completed in parallel, but the energy consumption increases substantially
Solution Approach 1:
The tag memory is divided into multiple ways, and the tag lookup process is segmented into multiple phases. In each phase, only a subset of ways is accessed based on partial tag matching, rather than accessing all ways in parallel. This segmentation reduces the number of simultaneously active memory accesses, thereby reducing energy consumption while maintaining lookup functionality.
Solution Approach 2:
The tag lookup process performs preliminary actions by first comparing a portion of the incoming tag with tags in a subset of ways before accessing the complete tag memory. This preliminary comparison allows the system to identify candidate ways that may contain the desired data, enabling subsequent targeted accesses and avoiding unnecessary energy expenditure on ways that cannot contain the target address.
2Loss of energy
If tag way halting is implemented to reduce the number of bits accessed in each way, then power consumption is saved by not accessing the full tag address lookup, but the latency increases due to multiple access phases
Solution Approach 1:
The tag lookup is performed as a periodic multi-phase process rather than a single continuous operation. The lookup is divided into discrete phases where different portions of the tag are accessed at different times. This periodic action allows the system to manage power consumption by activating memory circuits only during specific phases rather than continuously, while the cumulative effect of all phases completes the full lookup functionality.
Solution Approach 2:
Preliminary comparison of tag portions is performed before committing to full way access. The system first evaluates partial tag matches to identify candidate ways, then proceeds to access only those candidate ways for complete tag verification. This preliminary filtering action reduces the average case latency and power consumption by avoiding full accesses to ways that will ultimately miss the lookup.
3Loss of energy
If a two-phase tag lookup process is used with preamble and prologue tag memories, then unnecessary memory accesses are minimized, but the device complexity increases
Solution Approach 1:
The tag memory subsystem is segmented into functionally distinct components: a first tag memory for storing initial tag portions and a second tag memory for storing remaining tag portions. This segmentation allows each memory component to be optimized independently and accessed selectively, reducing overall power consumption while distributing the complexity across modular units rather than requiring a single complex memory structure.
Solution Approach 2:
The system introduces intermediary control logic that manages the coordination between the first and second tag memories. This intermediary controller receives the incoming address, determines which tag portions to access first, manages the phase transitions, and coordinates the selective activation of different memory ways. While this adds control complexity, it enables sophisticated power management and reduces the complexity of individual memory components.
Data Source
AI summary
A memory subsystem can include a preamble tag memory and one or more prologue tag memories for one or more ways. The preamble tag memory includes hit circuitry. The preamble tag memory stores a set of bits from a tag portion of a plurality of addresses stored at the memory subsystem. The preamble memory hit circuitry performs a comparison of preamble bits of a received address and the stored set of bits from the tag portion in the preamble tag memory. Each prologue tag memory includes hit circuitry. The prologue tag memories store a remaining set of bits from the tag portion and memory data information of the plurality of addresses. The prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored remaining set of bits from the tag portion in that prologue tag memory.