Cache Tile Dimensioning for Compute Shader Multi-Pass Rendering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tiled caching in graphics processing units (GPUs) is limited in multi-pass rendering scenarios, particularly when render targets do not have a 1:1 correspondence between pixels, leading to substantial memory bandwidth consumption and reduced system performance due to the need for off-chip memory access operations.
Innovation Solution
A method to generate cache tiles by determining dimensions based on compute tiles, allowing data from compute shaders to be cached across multiple sub-passes, thereby reducing the need for off-chip memory access and improving memory bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If tiled caching is implemented in multi-pass rendering with 1:1 pixel correspondence, then memory bandwidth utilization is improved, but the applicability is limited to specific rendering scenarios
Solution Approach 1:
The patent changes the fundamental parameter of cache tile dimensioning from fixed screen-space coordinates to compute tile-based coordinates. By receiving first dimension information associated with a first compute tile and causing a tiler to assign dimensions to a first cache tile based on this compute tile dimension, the system adapts the cache structure to match the actual data access patterns of compute shaders, enabling tiled caching across diverse rendering scenarios including those without 1:1 pixel correspondence.
2Reliability
If off-chip memory access operations are performed for boundary pixels in compute shaders, then data accuracy is maintained, but system performance deteriorates due to substantial bandwidth consumption
Solution Approach 1:
The patent applies preliminary action by pre-loading compute tile data into cache tiles before the compute shader execution. The tiler assigns dimensions to cache tiles based on compute tile information, ensuring that all necessary data for a given compute tile is already resident in on-chip cache memory when the compute shader needs it. This eliminates the need for boundary pixels to perform off-chip memory access operations during execution, maintaining data accuracy while preventing bandwidth consumption penalties.
Data Source
AI summary
A device driver is configured to identify a group of compute shaders to be executed in multiple traversals of a graphics processing pipeline. Each such compute shader accesses a compute tile of data having particular dimensions. The device driver interoperates with a tiling unit to determines dimension for a cache tile so that an integer multiple of each compute tile will fit evenly within the cache tile. Thus, when executing compute shaders in different traversals of the graphics processing pipeline, the data processed by those compute shaders can be cached in the cache tile between passes.