Cache-to-Cache Intervention for Multiprocessor Data Handoff

Solution Overview

Problem

In multiprocessor data processing systems, the minimum handoff interval for sourcing a cache line from one vertical cache hierarchy to another is limited by the time between issuing a request and receiving a systemwide coherence response, leading to inefficiencies due to non-productive periods where processing units cannot initiate processing until the combined response is received.

Innovation Solution

Implementing cache-to-cache intervention to provide an early indication of the systemwide coherence response, allowing the first cache memory to initiate processing and source the target cache line before receiving the combined response, thereby reducing the handoff interval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system waits for the systemwide coherence response before initiating data handoff processing, then cache coherence reliability is ensured, but the handoff interval increases and system productivity decreases

Engineering Contradiction:

Improvecache coherence reliabilityVSAvoidsystem productivity

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by initiating data handoff processing before the systemwide coherence response is received. The first cache memory starts installing the target cache line and updating coherence states in advance, based on an early indication of the coherence response. This allows the handoff to proceed concurrently with coherence protocol completion, reducing the handoff interval while maintaining reliability through subsequent coherence response validation.

Inventive Principle:

Principle #10Preliminary action

2Speed

If the minimum handoff interval is reduced by initiating processing before receiving the combined response, then data transfer speed improves, but the risk of coherence violations increases

Engineering Contradiction:

Improvedata transfer speedVSAvoidcoherence protocol compliance

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements feedback by using the early indication of the systemwide coherence response to trigger preliminary handoff processing. The coherence protocol mechanism provides feedback about the likely outcome of the coherence request, which is then used to advance the data handoff. This feedback-driven approach allows the system to optimize timing while maintaining coherence guarantees through the structured coherence protocol framework.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by initiating data handoff processing before the systemwide coherence response is received. The first cache memory starts installing the target cache line and updating coherence states in advance, based on an early indication of the coherence response. This allows the handoff to proceed concurrently with coherence protocol completion, reducing the handoff interval while maintaining reliability through subsequent coherence response validation.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If processing units wait for the combined coherence response before initiating processing, then data accuracy is ensured, but latency in data transfer increases

Engineering Contradiction:

Improvedata accuracyVSAvoidlatency in data transfer

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by initiating data handoff processing before the systemwide coherence response is received. The first cache memory starts installing the target cache line and updating coherence states in advance, based on an early indication of the coherence response. This allows the handoff to proceed concurrently with coherence protocol completion, reducing the handoff interval while maintaining reliability through subsequent coherence response validation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10102130B2Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response

Publication Date: 2018.10.16 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.