Cache Transfer List for Processor Failover Latency
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Solution Overview
Problem
In storage systems with multiple processor nodes, failover operations lead to significant latency in processing read/write requests due to the need to read track metadata from storage, especially after a failover event, where the surviving processor node lacks track format information for reassigned storage areas.
Innovation Solution
The failing processor node transfers track format information, including track format codes, to the surviving processor node during failover, allowing the surviving node to maintain this information for subsequent I/O requests, thereby reducing the need to read metadata from storage and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the surviving processor node reads track metadata from storage after failover, then it can obtain track format information, but significant latency is introduced
Solution Approach 1:
The failing processor node performs preliminary action by transferring track format information to the surviving processor node before the failover is complete. This advance preparation ensures that when the surviving node takes over, the metadata is already available in memory, eliminating the need to read from storage and thus reducing latency.
Solution Approach 2:
A cache transfer list structure serves as an intermediary mechanism between the failing and surviving processor nodes. This intermediary carries track format information during the failover process, allowing the surviving node to acquire metadata without direct storage access, thereby bridging the information gap efficiently.
2Productivity
If track format information is transferred during failover, then latency is reduced, but additional processing steps are required
Solution Approach 1:
The patent merges the track format information transfer with the existing cache transfer process during failover. By combining these operations into a unified cache transfer list structure, the system avoids adding separate complex mechanisms while still achieving the benefit of pre-transferred metadata.
Solution Approach 2:
The failing processor node automatically transfers its cache information including track format data to the surviving node as part of the failover sequence. This self-service approach eliminates the need for external intervention or complex coordination, reducing overall system complexity while maintaining high productivity.
3Reliability
If all cache information is transferred during failover, then the surviving node can handle requests immediately, but transfer time and bandwidth are increased
Solution Approach 1:
The patent extracts only the essential track format information from the complete cache data and transfers it to the surviving processor node. This selective extraction of critical metadata (track identifiers, format codes, layout information) rather than entire cache contents reduces transfer time and bandwidth requirements while ensuring the surviving node has sufficient information to handle I/O requests immediately.
Data Source
AI summary
Provided are a computer program product, system, and method for managing failover from a first processor node including a first cache to a second processor node including a second cache. Storage areas assigned to the first processor node are reassigned to the second processor node. For each track indicated in a cache list of tracks in the first cache for the reassigned storage areas, the first processor node adds a track identifier of the track and track format information indicating a layout and format of data in the track to a cache transfer list. The first processor node transfers the cache transfer list to the second processor node. The second processor node uses the track format information transferred with the cache transfer list to process read and write requests to tracks in the reassigned storage areas staged into the second cache.