Cache Memory Transient Storage Eviction Bandwidth

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Solution Overview

Problem

In cache memory systems, transient data that is evicted from the cache is not written to the backing memory, leading to increased bandwidth and memory footprint requirements, as well as higher power consumption, since this data must be re-generated if needed again.

Innovation Solution

Implementing transient storage using separate hardware, such as RAM, that maps one-to-one with cache entries, allowing for efficient storage and retrieval of transient data without writing it to the backing memory, thereby reducing bandwidth and memory footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If transient data is evicted from cache without writing to backing memory, then bandwidth and power consumption are reduced, but data must be re-generated if needed again

Engineering Contradiction:
Improvepower consumptionVSAvoidtransient data
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

The patent extracts transient data from the traditional cache-eviction-to-backing-memory path by introducing a separate transient storage structure. This allows transient data to be handled independently from permanent cache data, enabling selective eviction without writing to backing memory while maintaining the ability to regenerate only when absolutely necessary.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the cache storage into distinct components: regular cache entries and transient storage fields. This segmentation allows different eviction policies to be applied to different data types, with transient data being evicted without backing memory writes while regular cache data follows traditional policies.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If transient data is stored in separate hardware, then bandwidth and memory footprint are reduced, but device complexity increases

Engineering Contradiction:
Improvememory footprintVSAvoidhardware structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges transient storage fields with existing cache entry structures, allowing transient data to coexist with regular cache data in a unified memory structure. This integration approach reduces the need for completely separate hardware while still providing distinct storage paths for transient and permanent data.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The cache memory structure is designed to serve multiple functions: storing both permanent and transient data, supporting different eviction policies, and maintaining backward compatibility with existing cache protocols. The same memory infrastructure handles both data types, reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11023162B2Cache memory with transient storage for cache lines
Publication Date: 2021.06.01 APPLE INC
  • US11023162B2 patent drawing
  • US11023162B2 patent drawing
  • US11023162B2 patent drawing

AI summary

Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.