Cache Utilization Monitoring for Dynamic Power State Control
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Solution Overview
Problem
Higher level caches in processor architectures consume unnecessary power and introduce delays due to unfruitful searches when cache hit rates are low, as they remain active regardless of utilization.
Innovation Solution
Enabling and disabling higher level caches based on the utilization of lower level caches, using monitoring techniques such as cache hit rate, eviction rate, and suspend operation frequency to predict and adjust the power state of higher level caches, thereby reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher level caches are kept active continuously, then cache availability is improved, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies dynamics by making the cache hierarchy configurable rather than fixed. The system dynamically adjusts which caches are active based on runtime conditions (hit rates, miss patterns) allowing the transition between different cache activation states to optimize both availability and power consumption.
Solution Approach 2:
The patent changes operational parameters by modifying the activation state of higher level caches based on monitored performance metrics. When hit rates indicate low utilization, the system changes the parameter by disabling those caches, thereby reducing power consumption while maintaining adequate availability through lower level caches.
2Speed
If higher level caches are kept active continuously, then data access speed is improved, but processing delays increase due to unfruitful searches
Solution Approach 1:
The system dynamically reconfigures the active cache hierarchy based on observed access patterns. When higher level caches show low hit rates indicating unfruitful searches, the system disables them to eliminate the time penalty of searching inactive caches, while lower level caches maintain sufficient performance.
Solution Approach 2:
The patent extracts or removes the higher level caches from the active configuration when they are underutilized. By taking out these caches from the operational hierarchy, the system eliminates the delay associated with searching them while retaining the beneficial fast access of lower level caches.
3Use of energy by moving object
If lower level caches are used exclusively, then power consumption is reduced, but cache hit rate decreases
Solution Approach 1:
The system dynamically adjusts the cache hierarchy configuration based on runtime performance monitoring. When lower level caches achieve sufficient hit rates, the system activates higher level caches to improve overall hit rate, and deactivates them when hit rates drop, thereby optimizing the balance between power consumption and reliability.
Data Source
AI summary
A second cache (e.g., L2 cache) is enabled or disabled based at least in part on an utilization of a first cache (e.g., L1 cache). The utilization of the first cache may be interpreted as an estimation of the likely utilization of the second cache. The utilization may be estimated by monitoring, for example, the eviction rates of the first cache or other caches, by monitoring the proportion of ways of the first cache used by an instruction stream, or by monitoring the duration between certain instructions executed by the processor, such as the duration between suspend operations.