Cache Memory Soft Error Resistance via Local Voltage Segmentation

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Solution Overview

Problem

Caches in data processing systems are prone to soft errors due to increased sensitivity with technology scaling and low power states, which contribute to higher standby leakage power and unrecoverable loss of modified data.

Innovation Solution

The solution involves partitioning memory into more and less soft error-resistant locations, with modified data stored in error-resistant areas by increasing voltage across bitcells and disabling drowsy mode, while unmodified data is stored in less error-resistant areas to conserve power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If cache memory operates in low power state to reduce standby leakage power, then power consumption is reduced, but soft error rate increases

Engineering Contradiction:

Improvestandby leakage powerVSAvoidsoft error rate

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The cache memory is divided into multiple ways (e.g., 4 ways), with at least one way designated as a soft error resistant way. This segmentation allows the system to maintain full cache capacity while providing enhanced protection for specific data storage locations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The soft error resistant way operates at a higher voltage level compared to other ways, creating local quality differentiation. This voltage differentiation provides improved soft error resistance specifically where needed, while other ways can operate at lower voltages to conserve power.

Inventive Principle:

Principle #3Local quality

2Productivity

If modified data is stored in cache to improve processor performance, then processing speed is improved, but data loss due to soft errors becomes unrecoverable

Engineering Contradiction:

Improveprocessor performanceVSAvoiddata loss risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system proactively stores modified data in the soft error resistant way before any error can occur. By anticipating the vulnerability of modified data and preemptively placing it in protected storage, the system prevents potential data loss while maintaining normal cache operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The soft error resistant way acts as an intermediary storage location that provides enhanced protection for modified data. This specialized storage path mediates between the need for fast cache access and the need for data protection, allowing modified data to be stored safely while maintaining cache performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If voltage across bitcells is increased to improve soft error resistance, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of uniformly increasing voltage across all cache memory, the invention applies higher voltage only to the soft error resistant way. This localized voltage enhancement provides improved reliability where needed while avoiding the power penalty of increasing voltage across the entire cache.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system applies voltage enhancement partially, only to the extent necessary for soft error resistant storage. By providing more than enough protection for modified data in the dedicated way while keeping other ways at standard voltage, the system achieves adequate protection with minimal power overhead.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes soft error rates by limiting additional leakage power expenditure to only modified data, providing variable soft error resistance and adjustable memory locations, thus protecting modified data against errors while saving power.

Implementation Method 1

storing modified data in a more soft error resistant memory location compared to unmodified data by increasing a voltage across the bitcells of the memory

Methodology Applied

Scientific EffectVoltage increase effect:

Implementation Method 2

the cache memories are often retained in a low power state during an inactive state. This low power state is known to contribute towards increasing the soft error rate (SER)

Methodology Applied

Scientific EffectDrowsy mode effect:

Data Source

PatentUS9141552B2Memory using voltage to improve reliability for certain data types

Publication Date: 2015.09.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.