Cache Warm-Up Using Unwritten Range Detection

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Solution Overview

Problem

Current memory systems face inefficiencies in cache warm-up, particularly after a cold reset, where initial write requests often result in misses in the near memory, leading to unnecessary data fetches from the slower far memory, causing performance bottlenecks and power consumption issues.

Innovation Solution

Implementing a two-level memory system with a near memory (NM) and far memory (FM) where an indicator bit in a tag array determines if a memory request corresponds to an unwritten range, allowing the system to selectively avoid fetching data from the FM if it's unwritten, thereby writing zeros to the NM instead, thus speeding up cache warm-up and reducing data traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system performs traditional cache warm-up by fetching data from far memory after a cold reset, then the near memory cache is populated, but it causes unnecessary data traffic and power consumption due to fetching unwritten ranges

Engineering Contradiction:
Improvecache warm-up speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The system performs preliminary action by setting indicator bits during the cold reset to mark which memory ranges have been written. This preliminary marking allows the cache warm-up process to subsequently identify and skip unwritten ranges, avoiding unnecessary data fetching and power consumption while still populating the cache with valid data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory space is segmented into multiple ranges, each with an associated indicator bit that tracks whether the range has been written. This segmentation allows the system to selectively warm up only the necessary cache ranges rather than fetching all possible data, thereby reducing power consumption and data traffic during cache warm-up.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the system fetches all data from far memory to populate near memory cache, then the cache is fully warm, but it creates performance bottlenecks due to the slower access speed of far memory

Engineering Contradiction:
Improvesystem performanceVSAvoidcache warm-up time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The indicator bits are set in advance during cold reset to identify unwritten memory ranges. During cache warm-up, the system checks these pre-set indicators and skips fetching data from unwritten ranges in the far memory, thereby reducing cache warm-up time and eliminating performance bottlenecks caused by slow far memory access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of performing a complete cache warm-up by fetching all possible data from far memory, the system performs partial action by fetching only the necessary written ranges. This selective approach reduces the time spent accessing slow far memory while still achieving sufficient cache population for optimal system performance.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If the system reads from far memory during initial writes after cold reset, then data is available for writing, but it generates unnecessary data traffic since the ranges are unwritten

Engineering Contradiction:
Improvewrite operation efficiencyVSAvoiddata traffic
Core Design Contradiction:
Ease of operationVSLoss of substance

Solution Approach 1:

The system performs preliminary action by setting indicator bits during cold reset to mark unwritten memory ranges. During write operations, the system checks these pre-set indicators and skips reading from unwritten ranges in the far memory, thereby eliminating unnecessary data traffic while maintaining efficient write operation performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10372609B2Fast cache warm-up
Publication Date: 2019.08.06 INTEL CORP
  • US10372609B2 patent drawing
  • US10372609B2 patent drawing
  • US10372609B2 patent drawing

AI summary

An embodiment of a semiconductor package apparatus may include technology to determine if a memory request for a second level memory results in a miss with respect to a first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten, if the memory request results in the miss with respect to the first level memory, and blank a corresponding range of the first level memory if the range of the second level memory corresponding to the memory request is determined to be unwritten. Other embodiments are disclosed and claimed.