Configurable Cache Way Allocation for Multi-Core Memory Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and outdated data, particularly when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces and an external memory master interface, allowing for efficient management of memory access requests and coherency through hardware-based snoop filtering and cache tag management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to maintain coherency, then data coherence can be achieved, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically monitors and maintains cache coherency. The coherency controller uses hardware circuits to detect cache hits, invalidate stale data, and coordinate between cores, eliminating the need for software intervention and thereby improving operational efficiency while maintaining data coherence.
Solution Approach 2:
The coherency controller enables the multi-core system to automatically maintain cache coherency without external software management. The controller continuously monitors cache states, detects coherence violations, and executes corrective actions autonomously, allowing the system to self-manage coherency and freeing up software resources for other tasks.
2Adaptability or versatility
If multiple processing cores access the same memory address simultaneously, then system functionality is enhanced, but coherency issues arise leading to outdated data
Solution Approach 1:
The coherency controller implements a feedback mechanism where it continuously monitors memory access requests from multiple cores and cache states. When a coherence violation is detected (e.g., one core modifies data while another has stale cached data), the controller sends feedback signals to invalidate or update the appropriate cache entries, ensuring all cores access consistent data.
Solution Approach 2:
The coherency controller acts as an intermediary between multiple processing cores and the shared memory system. It intercepts memory access requests, coordinates between cores to maintain coherency, and manages cache validity states, thereby enabling simultaneous multi-core access while preventing data inconsistency.
3Speed
If a core modifies cached data without committing back to shared memory, then access speed is improved, but data coherence deteriorates causing other cores to receive outdated data
Solution Approach 1:
The coherency controller performs preliminary actions by setting up coherency monitoring and validation mechanisms before data access operations occur. It pre-establishes coherence protocols and tracks which cores have modified cached data, so when coherence issues arise, the controller can quickly resolve them without sacrificing the speed benefits of cached access.
Data Source
AI summary
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.