Configurable Cache-Way Allocation for Coherent Multi-Core Memory

The patent introduces a memory controller as an intermediary between multiple processing cores and shared memory. The memory controller implements snoop filter logic that monitors and coordinates access to shared memory addresses, ensuring that cache coherency is maintained while allowing concurrent access from multiple cores. This mediator resolves the conflict between parallel access and data consistency by managing the interaction between cores and memory.

The patent replaces software-based cache maintenance operations with hardware-based snoop filter logic integrated into the memory controller. The snoop filter uses hardware logic to automatically monitor memory access requests, identify cache hits, and manage coherency protocols without requiring software intervention. This substitution eliminates the performance overhead of software operations while maintaining data consistency.

The snoop filter logic selectively issues snoop requests only when necessary - specifically when a cache hit is detected and coherency might be compromised. Rather than issuing snoop requests for every memory access, the filter analyzes access patterns and generates snoop requests only for cases where data consistency could be affected. This partial action approach maintains coherency while minimizing the time loss associated with snoop operations.