Cache Way Group Mapping for Multi-Feature Interference
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Solution Overview
Problem
Existing cache systems face interference issues when multiple cache features are applied to individual way groups, leading to performance and energy consumption problems.
Innovation Solution
Implementing first and second mappings for cache way groups to prevent interference between cache feature circuitries, allowing each feature to access at least one cache way regardless of the actions taken by the other feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple cache features are applied to individual way groups, then energy consumption benefits and performance improvements can be realised, but interference between cache features occurs that prevents them from operating as intended
Solution Approach 1:
The patent segments the cache ways into different way groups for different cache features. Each cache feature operates on its own dedicated way groups, preventing interference. For example, first cache feature operates on way groups formed from first set of cache ways, while second cache feature operates on way groups formed from second set of cache ways, ensuring independent operation.
Solution Approach 2:
The patent applies different mappings locally to different cache features. Each cache feature has its own mapping configuration that defines which cache ways belong to its way groups. This local customization allows each feature to optimize its operation without affecting others, with first mapping for first cache feature and second mapping for second cache feature.
2Device complexity
If multiple cache features share the same way group mapping, then device complexity is reduced, but one cache feature cannot access cache ways when another feature applies actions to those way groups
Solution Approach 1:
The patent implements dynamic mapping selection based on which cache feature is active. The system switches between first mapping and second mapping depending on the operational requirements of different cache features. This dynamic approach allows the same physical cache ways to be logically reorganized for different features, ensuring each feature can access its required cache ways.
Solution Approach 2:
The patent adds a mapping dimension to the cache architecture, creating multiple mapping configurations (first mapping, second mapping, etc.) that can be selected based on the active cache feature. This dimensional approach allows the same physical cache structure to support multiple feature configurations without increasing physical complexity.
Data Source
AI summary
An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups. The first mapping and the second mapping are selected so as to prevent application of a cache feature to the way groups by one of the cache feature circuits from interfering with the ability of the other cache feature circuit to access at least one cache way in each of the way groups. Such an approach alleviates the risk of actions taken by one of the cache features from interfering with the ability of the other cache feature to operate as intended.