Cache Way ID for Near Memory Write Back Efficiency
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Solution Overview
Problem
In two-level memory systems, traditional write back operations in near memory often require multiple read accesses, increasing latency and reducing efficiency due to the lack of way ID information in cache blocks, which complicates identifying the correct cache block for updates.
Innovation Solution
Incorporating a way ID and an inclusive bit in cache lines of the last level cache to determine the location of cache blocks within near memory, allowing direct write operations without the need for additional read operations during write back processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional write back operations are performed in near memory without way ID information, then the system can maintain simpler cache block structures, but multiple read accesses are required increasing latency and reducing write back efficiency
Solution Approach 1:
The patent applies preliminary action by storing the way ID in the cache block header during the cache fill operation (before the write back is needed). This pre-stored way ID information is then readily available during write back operations, eliminating the need for additional read accesses to determine the correct cache block location, thereby reducing latency and improving write back efficiency
Solution Approach 2:
The way ID stored in the cache block header acts as an intermediary that bridges the cache controller and the near memory. Instead of directly querying near memory to find the correct block during write back, the controller uses the pre-stored way ID to directly identify and write to the correct cache block, reducing the number of access operations required
2Productivity
If way ID information is stored in cache blocks, then direct write operations can be performed reducing near memory read operations, but the cache block structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the cache block into distinct components: the cache block header (containing the way ID and other control information) and the cache block data (the actual stored data). This segmentation allows the way ID to be stored separately in the header, making the complexity isolated to a small metadata area rather than affecting the entire cache block structure, thus minimizing the impact on overall system complexity while enabling efficient direct writes
Data Source
AI summary
One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.