Cache Way-Locking for Independent Multi-Context Execution Traces

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Solution Overview

Problem

Existing processor-based tracing techniques cannot record simultaneous/interleaved execution of plural execution contexts into separate and distinct replayable traces, particularly when these contexts interact with common shared memory, due to the inability to determine the appropriate trace data stream for logging cache line data.

Innovation Solution

Implement cache way-locking and memory page markings to partition memory cache subsets and tag memory regions, enabling each execution context to have its own trace buffer, and log memory operations accordingly, ensuring each trace contains sufficient data for independent replay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If processor-based tracing techniques log cache line data for simultaneous execution contexts, then execution traces can be recorded, but the ability to determine the appropriate trace data stream is lost when contexts interact with common shared memory

Engineering Contradiction:
Improvetrace dataVSAvoidtrace data stream identification
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the memory cache into separate cache subsets, with each subset locked to a specific execution context. This segmentation allows the system to track which execution context owns which cache data, enabling proper trace data stream identification even when multiple contexts interact with shared memory regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces cache way-locking as an intermediary mechanism between execution contexts and cache memory. This locking mechanism acts as a mediator that tracks ownership and determines the appropriate trace data stream for logging, resolving the ambiguity of which trace should receive data from shared memory accesses.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If all execution contexts are recorded into a common trace buffer, then tracing is simplified, but separate and distinct replayable traces for each context cannot be produced

Engineering Contradiction:
Improvetracing systemVSAvoidindependent trace replay capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent divides the single trace buffer into multiple separate trace buffers, with each buffer dedicated to recording a specific execution context. This segmentation enables independent replay capability for each context while maintaining a relatively simple tracing system architecture through the use of cache way-locking.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If cache way-locking is implemented to partition memory cache subsets, then independent trace recording is enabled, but device complexity increases

Engineering Contradiction:
Improveindependent trace recordingVSAvoidprocessor architecture
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent uses cache way-locking as an intermediary mechanism that leverages existing cache architecture features. By implementing locking at the cache way level rather than requiring complete architectural redesign, the system enables independent trace recording with minimal increase in device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12475055B2Processor support for using cache way-locking to simultaneously record plural execution contexts into independent execution traces
Publication Date: 2025.11.18 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12475055B2 patent drawing
  • US12475055B2 patent drawing
  • US12475055B2 patent drawing

AI summary

Using way-locking to record plural execution contexts into independent execution traces. A processor partitions a cache into a first subset of ways that are locked to a first context recorded into a first trace and a second subset of ways that are locked to a second context recorded into a second trace. The processor also detects a memory operation by the first context into the second cache subset. The processor then performs at least one of: when the memory operation causes an influx into the second cache subset, initiating logging of the influx to the second trace; when the memory operation is a read from the second cache subset, initiating logging of the read to the first trace; or when the memory operation is a write to the second cache subset, performing one of initiating logging of the write to the second trace, or evicting a target cache line.