Cache Way Identification Using Microtag and Micro TLB
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Solution Overview
Problem
Accessing data in caches is inefficient due to the need for large and complex addresses, which requires significant power and time, especially in set associative caches where virtual addresses need to be converted to physical addresses using a translation lookaside buffer, and the comparison of tags can be slow and power-intensive.
Innovation Solution
A data processor that uses a μTLB to store mappings of virtual to physical addresses and a μTAG store to identify recent cache accesses, allowing only a portion of the address to be stored and compared, leveraging the μTLB's higher order bits to determine the cache way, thereby reducing power consumption and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual addresses are converted to physical addresses using a translation lookaside buffer, then accurate address translation is achieved, but the conversion process is slow and increases power consumption
Solution Approach 1:
The patent applies preliminary action by pre-storing the cache way information in the μTAG store before the actual cache access occurs. The μTAG store captures and stores the cache way identifier when a cache access happens, so that when a subsequent access request comes in, the cache way information is already available for immediate use, eliminating the need for slow real-time determination.
Solution Approach 2:
The patent introduces an intermediary mechanism by using the μTAG store as a mediator between the virtual address translation process and the cache access process. The μTAG store acts as an intermediate storage that holds cache way information, allowing the system to bypass the slow virtual-to-physical address conversion when determining cache way, thus resolving the speed-accuracy tradeoff.
2Measurement precision
If full addresses are stored and compared to identify cache ways, then accurate cache way identification is achieved, but power consumption and processing time increase significantly
Solution Approach 1:
The patent applies the extraction principle by extracting only the necessary cache way identification information from the full address and storing it separately in the μTAG store. Instead of storing and comparing entire virtual or physical addresses, the system extracts just the cache way identifier (a small number of bits) and stores that in the μTAG store, dramatically reducing the amount of data that needs to be processed and compared.
Solution Approach 2:
The patent segments the address into different components: the virtual address for translation, the physical address for access, and the cache way identifier for selection. By separating the cache way identification function from the full address handling, the system can process only the relevant cache way bits rather than the entire address, reducing power consumption while maintaining accuracy.
3Reliability
If multiple cache ways are enabled for access, then data can be retrieved from any valid cache way, but power consumption increases due to enabling multiple ways
Solution Approach 1:
The patent applies preliminary action by determining which cache way contains the required data before actually enabling that way for access. The μTAG store is updated in advance with the correct cache way identifier, allowing the system to enable only the necessary cache way rather than enabling all ways and then searching, thus reducing power consumption while maintaining reliable data access.
Solution Approach 2:
The patent applies local quality by making the cache way selection specific to each access request rather than using a uniform approach. The μTAG store provides cache way information that is tailored to the specific memory location being accessed, allowing the system to enable only the relevant cache way for that local access pattern, optimizing power consumption while ensuring reliable data retrieval.
Data Source
AI summary
A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one of said plurality of recently accessed cache storage locations and if so to identify a cache way of said cache storage location from data stored in both said data store and said table.