Multi-Level Cache Write Allocate Pipelining With Data Merging
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Solution Overview
Problem
In multi-level cache systems, write requests that result in cache misses lead to inefficiencies as they stall the CPU and higher cache levels, preventing pipeline processing and resulting in lost soft error protection due to delayed parity and error correction information commitment.
Innovation Solution
The cache controller handles write request cache misses by storing write data and sending a read request to external memory, merging the write data with returned data, and storing it in buffers, allowing for continued processing of other requests while waiting for external memory responses, and enabling soft error protection by generating parity/error correction information during writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache controller processes write allocate requests sequentially and waits for external memory response before servicing other requests, then data integrity and error protection are maintained, but CPU and cache levels are stalled causing loss of productivity
Solution Approach 1:
The cache controller performs preliminary actions by storing write data in buffer entries and initiating read requests to external memory in advance. The write data is held in buffers with associated metadata (address, position, unique ID) ready for merging, allowing the system to proceed with processing other requests while the memory operation completes in the background.
Solution Approach 2:
Buffers serve as intermediary storage between the write requestor and external memory. The buffer entries hold write data and control information, enabling the cache controller to decouple the write operation from the external memory access. This intermediary mechanism allows continuous processing while maintaining data integrity through controlled merging of write data with returned cache lines.
2Reliability
If the cache controller waits for the allocated cache line to be fully stored before writing data into it, then error detection and correction information is preserved, but processing time is increased reducing productivity
Solution Approach 1:
Write data is preliminarily stored in buffer entries with associated control information before the external memory operation completes. The buffer holds the write data ready for merging, eliminating the need to wait for cache line allocation before data is prepared. This preliminary preparation reduces latency while maintaining reliability through controlled merging operations.
Solution Approach 2:
The cache controller maintains continuous useful action by processing multiple requests through pipelining. While one write allocate is pending external memory response, other requests can be serviced. The buffer mechanism enables continuous data preparation and merging operations without idle waiting periods, maintaining high utilization of the cache controller.
3Device complexity
If the cache controller processes only one allocate request at a time, then resource management is simplified, but the system cannot pipeline multiple requests reducing productivity
Solution Approach 1:
The cache controller is segmented into multiple buffer entries, each capable of holding write data and control information for a separate request. This segmentation allows the controller to manage multiple requests in parallel through distinct buffer slots, enabling pipelining without requiring complex reconfiguration of the control logic. Each buffer entry operates as an independent container for its associated request.
Solution Approach 2:
The buffer structure serves multiple functions: storing write data, holding control information (address, position, unique ID), enabling pipelining of multiple requests, and facilitating merging operations. This universal buffer mechanism handles various request types and states without requiring separate specialized logic for each function, maintaining relatively simple controller design while achieving high throughput.
Data Source
AI summary
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data returned from the external memory and stores merged data in the cache. The cache controller includes buffers with plural entries storing the write address, the write data, the position of the write data within a cache line and unique identification number. This stored data enables the cache controller to proceed to servicing other access requests while waiting for response from the external memory.