Cached Convolution Neural Network for Low-Power Time-Series Classification
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Solution Overview
Problem
Current artificial neural networks face challenges in efficiently processing and classifying continuous, real-time data streams due to high computational and power requirements, particularly in maintaining accurate and timely responses for applications like speech recognition and image classification.
Innovation Solution
The proposed neural network architecture incorporates caching of convolutions for time-dependent activation data, utilizing single-port SRAM for activation data memory and optimized hardware operations to process data incrementally, allowing for real-time classification with reduced power consumption and increased performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional neural networks process continuous data streams in real-time, then classification accuracy is maintained, but power consumption and computational requirements increase significantly
Solution Approach 1:
The patent pre-calculates and caches convolution results for all possible input combinations before real-time inference. During runtime, the system retrieves pre-computed activation values from cache memory rather than performing full convolutions, dramatically reducing power consumption while maintaining classification accuracy for continuous data streams
Solution Approach 2:
The system dynamically adapts its processing mode based on input data characteristics. For time-dependent sequential data, it activates cached convolution retrieval paths; for static data, it uses standard inference paths. This dynamic adaptation optimizes power consumption while preserving accuracy across different data types
2Use of energy by moving object
If cached convolutions are used for time-dependent activation data, then power consumption is reduced, but memory requirements increase
Solution Approach 1:
The patent segments the caching memory into multiple specialized buffers: input activation buffers, output activation buffers, and filter weight buffers. Each buffer is optimized for specific data types and access patterns, reducing total memory requirements compared to a monolithic cache while enabling selective caching of only necessary convolution results
Solution Approach 2:
The system dynamically adjusts cache retention parameters based on data characteristics. For time-dependent sequential data with temporal correlations, it extends cache retention periods; for independent data points, it uses shorter retention. This parameter adaptation reduces memory volume requirements while maintaining power efficiency benefits
3Loss of time
If incremental processing is implemented for real-time data streams, then response time is improved, but processing complexity increases
Solution Approach 1:
The patent segments the neural network into modular processing stages with dedicated input buffers, processing units, and output buffers. Each stage processes data incrementally and independently, enabling real-time responses without requiring complex coordination between processing elements. The modular architecture manages complexity through clear separation of concerns
4Speed
If single-port SRAM is used for activation data memory, then access speed is improved, but memory capacity is reduced
Solution Approach 1:
The patent divides the activation memory into multiple single-port SRAM banks, each dedicated to specific data types (input activations, output activations, intermediate results). This segmentation enables parallel access across banks, achieving high effective bandwidth while maintaining the speed benefits of single-port SRAM. The total capacity is distributed across banks rather than concentrated in a single large memory
Data Source
AI summary
A data classification engine includes an interface configured to interface with an input source, where the input source includes sequential data points representative of a time-varying input signal and one or more processors adapted to receive a temporal sequence of data points at a time T, where the one or more processors are further adapted to receive a next sequential data point and facilitate discarding an oldest data point of the temporal sequence at a time T+1. The data classification engine further includes a matrix adapted to align, at time T, to successive temporal portions of the temporal sequence to generate a set of successive outputs from the temporal sequence and one or more memory modules adapted to store the set of successive outputs from the temporal sequence. The matrix is further adapted to align at time T+1 to another successive temporal portion that includes the next sequential data point to generate a successive output, wherein the one or more processors are adapted to use the successive output and the set of successive outputs of the temporal sequence excluding a temporal sequence from the set of successive outputs that includes the oldest data point to generate another set of successive outputs.