Cached Data Segmentation and Time Division Multiplexing for Read Write Overhead

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Solution Overview

Problem

Conventional data caching architectures in multi-threaded processors read and write data in whole frames, leading to increased data read and write time overhead and reduced processor utilization when multiple threads concurrently perform read and write tasks.

Innovation Solution

The method involves segmenting to-be-cached data into multiple pieces of fragmented data and writing them sequentially into independent storage blocks using a time division multiplexing manner, ensuring each piece is stored in a different storage particle, and saving the correspondence between data identifiers and storage addresses in a resource management table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is read and written in whole frames using conventional caching architecture, then data integrity is maintained, but data read and write time overhead increases and processor utilization decreases

Engineering Contradiction:
Improvedata integrityVSAvoiddata read and write time overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments data into multiple granularities (frames, sub-frames, and particles) and distributes them across multiple storage blocks. This allows concurrent read/write operations on different segments simultaneously, reducing time overhead while maintaining data integrity through the resource management table that tracks all segment locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of data organization by distributing data particles across multiple storage blocks with independent address buses and data buses. This multi-dimensional storage approach enables parallel access from multiple threads simultaneously, transforming sequential access into concurrent access and reducing time overhead.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a single cache space is used for data storage, then device complexity is reduced, but processor utilization decreases when multiple threads perform concurrent read and write tasks

Engineering Contradiction:
Improvecache space structureVSAvoidprocessor utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The cache space is segmented into multiple storage blocks, each with independent address and data buses. This segmentation allows multiple threads to access different storage blocks simultaneously without contention, improving processor utilization while maintaining manageable complexity through the resource management table that coordinates access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resource management table is pre-configured with the mapping relationships between data identifiers and storage block addresses before concurrent operations begin. This preliminary organization enables threads to access their required data particles directly without dynamic arbitration, improving processor utilization while keeping the storage structure relatively simple.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple storage blocks with independent address bus and data bus are used, then concurrent read and write operations are enabled, but device complexity increases

Engineering Contradiction:
Improveconcurrent operation capabilityVSAvoidstorage block configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The resource management table serves as an intermediary that manages the complexity of multiple storage blocks with independent buses. It maintains the mapping between data identifiers and storage locations, enabling concurrent operations without requiring complex hardware arbitration logic, thus balancing productivity improvement with acceptable device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12293113B2Method for storing and reading cached data and device
Publication Date: 2025.05.06 YUSUR TECH CO LTD
  • US12293113B2 patent drawing
  • US12293113B2 patent drawing
  • US12293113B2 patent drawing

AI summary

A method for storing and reading cached data and a device are provided. The method for storing and reading cached data includes: in response to receiving to-be-cached data, segmenting the to-be-cached data sequentially into at least two pieces of first fragmented data; writing the first fragmented data sequentially into first storage particles of at least two storage blocks in a time division multiplexing manner, and ensuring that the first fragmented data written into the respective first storage particles are different from each other. The fragmented data are stored and read in the time division multiplexing manner, and the fragmented data corresponding to a complete data are stored in different storage blocks, so a plurality of data can be stored and read in a complete data storage and read process, thereby reducing read and write time overhead during the execution of a large number of buffered data storage and read tasks.