Cached Memory Structure with SRAM Buffers for Flash Power Reduction
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Solution Overview
Problem
Flash memory technologies face limitations such as high power consumption and slow operation speed, while alternative non-volatile memory technologies like resistive random-access memory (ReRAM) and conductive bridging RAM (CBRAM) offer lower power and higher speeds but require innovative architectures and control methods to optimize performance.
Innovation Solution
The implementation of a cached memory device with SRAM buffers integrated within flash memory arrays, utilizing programmable impedance elements in resistive switching memory cells, and advanced buffer management techniques to enhance programming speed, endurance, and power efficiency, including dual buffering for frequent and occasional writes, and power fail management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory is used for non-volatile storage, then data retention and non-volatility are improved, but power consumption increases and operation speed decreases
Solution Approach 1:
The memory system is segmented into two distinct parts: flash memory for non-volatile data retention and SRAM buffers for volatile high-speed caching. This segmentation allows each component to operate in its optimal performance regime, with the SRAM handling frequent access patterns and the flash memory providing persistent storage, thereby reducing overall power consumption compared to using flash memory for all operations
Solution Approach 2:
SRAM buffers act as an intermediary layer between the CPU and flash memory. This intermediary captures and holds frequently accessed data, reducing the number of high-power flash memory operations required. The buffer mediates between the high-speed CPU and the slower, higher-power flash memory, improving overall system efficiency
2Duration of action of stationary object
If flash memory is used for non-volatile storage, then data retention is improved, but operation speed decreases
Solution Approach 1:
The memory hierarchy is segmented into SRAM buffers for high-speed operations and flash memory for data retention. By dividing the memory functionality, the system achieves both fast operation speeds for active data and reliable data retention for persistent storage
Solution Approach 2:
Data is pre-loaded into SRAM buffers from flash memory before being needed by the CPU. This preliminary action in the faster SRAM memory prepares data for quick access, reducing the time required for actual CPU operations and improving overall system speed
3Productivity
If resistive switching memory cells are used, then programming speed and power efficiency are improved, but architectural complexity increases
Solution Approach 1:
The patent introduces controller circuitry as an intermediary that manages the complex resistive switching memory cells. This controller handles the sophisticated write operations, state verification, and buffer management, shielding the rest of the system from the underlying complexity while enabling the high programming speeds and power efficiency of resistive switching technology
Solution Approach 2:
The memory system includes automatic buffer management and wear-leveling algorithms that operate without external intervention. The controller automatically monitors buffer states, performs wear-leveling across flash memory blocks, and manages data placement, reducing the burden on external controllers and simplifying system integration despite the inherent complexity of resistive switching cells
Data Source
AI summary
In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.