Storage Device Cached Physical Address Verification

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Solution Overview

Problem

In storage devices, cached physical addresses (PAs) from hosts are not guaranteed to be valid, requiring efficient validation mechanisms to ensure accurate data access in flash memory systems.

Innovation Solution

A storage device architecture that includes a descramble module to extract signature and physical address information from meta data, a compare module to validate the signature information against stored values, and an access module to verify the validity of the physical address for accessing flash memory, ensuring efficient validation and data retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the host caches physical address (PA) information to enable direct flash memory access, then access speed is improved, but the reliability of address validity deteriorates because cached PAs are not guaranteed to be valid

Engineering Contradiction:
Improvedata access speedVSAvoidaddress validity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing signature information in the flash memory before data access operations. When the host sends a read command with cached PA information, the storage device can immediately verify the cached PA's validity by comparing its generated signature against the pre-stored signature, eliminating the need for time-consuming LBA-to-PA conversion and ensuring address validity before access occurs

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces signature information as an intermediary element that mediates between the cached PA and the flash memory verification system. The signature acts as a compact representative of the LBA-PA mapping relationship, allowing the storage device to verify PA validity without performing full mapping lookups, thus maintaining both speed and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the storage device performs LBA to PA conversion for every read command, then address validity is ensured, but processing time increases

Engineering Contradiction:
Improveaddress validityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the essential verification element (signature information) from the complete LBA-PA mapping process. Instead of performing full LBA to PA conversion for every read command, the system extracts and compares only the signature portion, which is a compact representation of the mapping relationship. This extraction approach maintains address validity verification while dramatically reducing processing time

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the verification parameter from full LBA-PA mapping pairs to condensed signature information. By transforming the verification task from comparing complete address mappings to comparing compact signature values, the system achieves the same reliability goal with significantly reduced computational complexity and processing time

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11775423B2Storage devices that support cached physical address verification and methods of operating same
Publication Date: 2023.10.03 SAMSUNG ELECTRONICS CO LTD
  • US11775423B2 patent drawing
  • US11775423B2 patent drawing
  • US11775423B2 patent drawing

AI summary

A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.