Cached Parallel Packet Processing to Eliminate Waiting Time

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Solution Overview

Problem

Existing data packet processing systems experience reduced processing speed and efficiency due to the need to wait for all processing units to complete their operations on a previous data packet before starting on subsequent packets, especially with increasing data intersection information.

Innovation Solution

A data packet processing apparatus and method that utilizes a cache unit to store data packets and process them sequentially through multiple processing units in parallel, allowing simultaneous processing of next data packets based on descriptors, reducing waiting times and enhancing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple processing units sequentially process data packets in series, then processing order is maintained and correctness is ensured, but processing speed and efficiency deteriorate due to waiting for previous packets to complete

Engineering Contradiction:

Improveprocessing speedVSAvoidwaiting time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The cache unit pre-stores multiple data packets before processing begins, so that when processing units complete their current packet, subsequent packets are already available in the cache, eliminating waiting time and enabling continuous processing without idle periods

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

By maintaining a cache of pre-loaded data packets, the system ensures that processing units continuously have work available, eliminating idle waiting time between processing tasks and maintaining constant productive operation

Inventive Principle:

Principle #20Continuity of useful action

2Productivity

If the system waits for all processing units to complete current packets before starting next packets, then processing correctness is maintained, but productivity deteriorates due to idle waiting periods

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidinvalid waiting time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

Data packets are pre-loaded into the cache unit before processing starts, ensuring that when processing units finish their current tasks, subsequent packets are already ready in the cache, eliminating invalid waiting time and maintaining continuous productivity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cache unit acts as an intermediary buffer between data packet reception and processing units, decoupling the processing timeline from the packet arrival timeline, allowing processing units to continuously retrieve packets from cache without waiting for external input or completing all previous processing

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12566724B2Sequential processing method and apparatus of data packet

Publication Date: 2026.03.03 SPREADTRUM COMMUNICATION (SHANGHAI) CO LTD

AI summary

The present disclosure provides a data packet processing method and apparatus, when multiple data packets and descriptors are continuously received, the data packet processing apparatus stores the data packets in a cache unit, and the multiple data packets are processed respectively, by multiple processing units, in parallel and at the same time according to the descriptors of the multiple data packets.