PL-Side SMMU Address Translation for Cached SoC Logic Masters
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Solution Overview
Problem
Programmable logic (PL) masters in system-on-chip (SoC) designs face challenges with virtual-to-physical address translation, particularly for circuits with internal caches, as they cannot route their traffic through the processing system's system memory management unit (SMMU), leading to undesirable latency and inefficiencies.
Innovation Solution
A hardware-based virtual-to-physical address translation solution is implemented using a system memory management unit (SMMU) with an additional port for PL masters, featuring an address translator and interface operating in the PL clock domain, allowing direct address translation without routing through the processing system, thus eliminating clock domain crossing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PL masters route their traffic through the PS SMMU for address translation, then virtualization capability is provided, but latency increases and internal caches cannot operate efficiently
Solution Approach 1:
The SMMU is segmented into two independent interfaces: a PS interface for processing system masters and a PL interface for programmable logic masters. Each interface has its own translation buffer unit (TBU) that operates independently, allowing PL masters to access the SMMU directly without routing through the PS, thereby reducing latency while maintaining virtualization capability
Solution Approach 2:
A dedicated PL interface acts as an intermediary between PL masters and the SMMU address translation logic. This interface includes a PL-specific TBU that directly interfaces with PL masters through the interconnect, eliminating the need for traffic to route through the PS and reducing clock domain crossing latency
2Reliability
If PL masters with internal caches route traffic through the PS SMMU, then address translation is provided, but cache efficiency deteriorates due to inability to perform translation prior to cache access
Solution Approach 1:
The translation buffer functionality is segmented and duplicated: one TBU serves PS masters while another TBU serves PL masters with internal caches. This segmentation allows PL masters to access the SMMU directly and perform address translation before cache access, maintaining cache efficiency while ensuring address translation functionality
Solution Approach 2:
The PL interface enables preliminary address translation to occur before cache access by providing direct SMMU access to PL masters. The PL TBU can translate virtual addresses to physical addresses in advance, allowing the cache to operate efficiently with physical addresses without requiring PS routing
3Speed
If a dedicated PL interface with TBU is added to the SMMU, then address translation latency is reduced, but device complexity increases
Solution Approach 1:
The SMMU is designed with universal architecture where the PL interface reuses core SMMU components (address translation logic, page table structures) while adding only minimal PL-specific elements (PL TBU, PL interface logic). This multi-functionality approach reduces address translation latency while minimizing the increase in device complexity by leveraging existing shared resources
Data Source
AI summary
An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.