Formal Verification Using Cached Search Path Information
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Solution Overview
Problem
Conventional formal verification tools require extensive CPU-intensive computations and significant memory resources to identify unchanged portions of circuit designs, leading to inefficient processing times during multiple verification sessions.
Innovation Solution
The method involves storing counterexample traces and proof artifacts from previous sessions to quickly verify previously proven or disproven properties in subsequent sessions, using search-path verification processes that recreate the sequence of search operations to achieve proof objects or counterexamples, thereby reducing the need for expensive search processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional caching techniques use isomorphic graph checks and hash checks to identify unchanged circuit portions, then previously proven/disproven properties can be preserved, but extensive computations and significant memory resources (megabytes) are required at the beginning of each session
Solution Approach 1:
The patent extracts only the essential search path information (sequence of search operations, proof objects, counterexamples) from the full circuit verification process, storing only what is necessary to verify unchanged properties rather than entire circuit graphs or hash structures. This extraction reduces both computation and memory requirements while maintaining verification effectiveness.
Solution Approach 2:
The patent performs preliminary verification by checking whether stored search path information from previous sessions remains valid for current circuit versions. This preliminary check using stored proof objects and counterexamples allows the system to quickly determine if full verification is needed, avoiding extensive computations when circuits have not changed significantly.
2Reliability
If conventional formal verification tools perform CPU-intensive computations for every session to prove or disprove properties, then verification accuracy is maintained, but processing time becomes excessively long during regression mode and iterative debugging
Solution Approach 1:
The patent applies verification resources locally and selectively - storing and reusing search path information only for properties that have been proven or disproven in previous sessions. Instead of uniformly verifying all properties in every session, the system focuses computational resources only on properties whose status may have changed, maintaining accuracy while improving productivity.
Solution Approach 2:
The patent copies and reuses stored search path information (proof objects, counterexamples, search operation sequences) from previous verification sessions. By copying these verification results and checking their validity against current circuit versions, the system avoids redundant CPU-intensive computations while maintaining verification reliability through validation checks.
3Loss of time
If traditional caching techniques generate and compare isomorphic graphs for each design iteration, then unchanged portions can be identified, but significant memory space (megabytes) is required to store and compare these graphs
Solution Approach 1:
The patent uses lightweight, disposable search path information structures that can be quickly created and discarded. Instead of maintaining large isomorphic graphs in memory, the system stores compact verification traces and regenerates them only when necessary. This approach reduces memory space requirements while maintaining verification efficiency through selective regeneration of verification data.
Data Source
AI summary
A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved. The stored search path information is also utilized to perform efficient path-influenced search processes when the search-path verification process fails.