Cached Syndrome-Based Error Correction for NAND Flash

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Solution Overview

Problem

NAND flash memory devices face significant challenges in storage reliability due to noise sources like random-telegraph noise and inter-cell interference, which are exacerbated by aggressive technology scaling and multi-level per cell techniques, necessitating efficient error correction methods to maintain a non-recoverable bit error rate below 10−15.

Innovation Solution

Implementing a method to calculate and store error correction information in a cache based on syndromes, where the number of calculation cycles determines when to store the information, allowing for faster retrieval and reducing the need for time-consuming Berlekamp-Massey and Chien-search algorithms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction information is calculated using Berlekamp-Massey and Chien-search algorithms, then accurate error correction is achieved, but the calculation time and processor intensity increase significantly

Engineering Contradiction:
Improveerror correction accuracyVSAvoidcalculation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores error correction information for various syndrome patterns in a cache memory before actual error correction is needed. When errors occur, the system first checks if the syndrome matches pre-calculated patterns in the cache, avoiding time-consuming real-time computation of Berlekamp-Massey and Chien-search algorithms while maintaining accurate error correction

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates copies of frequently occurring error correction information and stores them in cache memory. Instead of recalculating the same error correction data repeatedly using complex algorithms, the system retrieves pre-computed copies from cache, significantly reducing calculation time while preserving correction accuracy

Inventive Principle:
Principle #26Copying

2Quantity of substance

If technology scaling and multi-level per cell techniques are used to reduce bit cost, then storage capacity increases, but storage reliability deteriorates due to increased noise sensitivity

Engineering Contradiction:
Improvestorage capacityVSAvoidstorage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the parameter of error correction aggressiveness based on the syndrome pattern. For syndromes indicating minor errors (common in scaled devices), simpler and faster correction methods are applied. For syndromes indicating complex errors, the full Berlekamp-Massey and Chien-search algorithms are used. This adaptive approach maintains reliability while improving speed for the majority of cases

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9594629B2Data error correction from cached error correction information
Publication Date: 2017.03.14 KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
  • US9594629B2 patent drawing
  • US9594629B2 patent drawing
  • US9594629B2 patent drawing

AI summary

A computing device for correcting data errors may receive data stored by a memory device; calculate a syndrome associated with the data; initiate a calculation of error correction information for the data based on the syndrome; search for the error correction information in a cache based on the syndrome; discontinue the calculation of the error correction information when the error correction information is found in the cache before the error correction information is calculated; and correct an error associated with the data using the error correction information from the cache.