Cacheless Memory Controller Data Transfer With CRC and MAC Protection
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Solution Overview
Problem
Existing memory systems face challenges in ensuring secure and reliable data transfer without the use of cache memory, particularly in the presence of attacks like row hammer attacks, while maintaining compliance with security protocols and error detection capabilities.
Innovation Solution
A memory controller operates without a cache, incorporating error detection and authentication capabilities, including cyclic redundancy code (CRC) and message authentication code (MAC), to ensure secure and reliable data transfer, with additional features like low-power chip kill (LPCK) and redundant array of independent disks (RAID) for error correction and protection against attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used for data transfer, then data transfer speed is improved, but security against row hammer attacks deteriorates
Solution Approach 1:
The patent removes the cache memory component from the memory controller entirely, extracting the vulnerability source that enables row hammer attacks. Data transfers occur directly between the host interface and memory interface without being cached, thereby eliminating the attack vector while maintaining functional data transfer capability.
Solution Approach 2:
The patent implements preliminary protective measures by incorporating authentication data and error correction codes before data leaves the memory controller. Message authentication codes (MAC) are generated for outgoing data, and error correction codes are applied to detect and correct potential corruption, creating defensive layers against attacks before they can exploit cache vulnerabilities.
2Reliability
If authentication and error correction mechanisms are added, then security and reliability are improved, but device complexity increases
Solution Approach 1:
The patent combines multiple protective functions into integrated operations within the memory controller. Authentication data generation, error correction coding, and data encryption/decryption are merged into the data path processing pipeline, allowing these security functions to operate concurrently with data transfer rather than as separate sequential steps.
Solution Approach 2:
The memory controller is designed with multi-functional components that handle both data transfer and security operations. The same hardware resources are used for authentication, error correction, and data routing, eliminating the need for dedicated separate circuits for each function and reducing overall device complexity.
3Object-affected harmful factors
If cache memory is removed, then security against row hammer attacks is improved, but data transfer efficiency may deteriorate
Solution Approach 1:
The patent performs preliminary data preparation by generating authentication codes and error correction data before the actual data transfer occurs. This allows the main data payload to be transferred without requiring post-transfer verification or retransmission, maintaining efficiency while enhancing security.
Solution Approach 2:
The patent maintains continuous data flow through the memory controller by processing authentication and error correction operations in parallel with data transfer. The useful action of data transmission continues uninterrupted while security functions operate simultaneously, preventing efficiency degradation despite the removal of cache memory.
Data Source
AI summary
A memory controller can operate to provide various data protection schemes without a need of a cache. A unit of data transfer between the memory controller and memory devices can correspond to a size of data corresponding to a host read and/or write command. The memory controller operating without a cache can still ensure data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).